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author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 10:53:44 -0700 |
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committer | GitHub <noreply@github.com> | 2019-10-08 10:53:44 -0700 |
commit | 4c89a4e642c8618a0e18270d338e48599834d923 (patch) | |
tree | 9cdc0a26a98880fd9f0f90e21db269d074901471 /passes | |
parent | 9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f (diff) | |
parent | 84f978bdc20494167a6a2c5f654b96c4f565a5e0 (diff) | |
download | yosys-4c89a4e642c8618a0e18270d338e48599834d923.tar.gz yosys-4c89a4e642c8618a0e18270d338e48599834d923.tar.bz2 yosys-4c89a4e642c8618a0e18270d338e48599834d923.zip |
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
async2sync to be called by equiv_opt only when -async2sync given
Diffstat (limited to 'passes')
-rw-r--r-- | passes/equiv/equiv_opt.cc | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index 4ab5b1a3e..c7e6d71a6 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -33,7 +33,7 @@ struct EquivOptPass:public ScriptPass log(" equiv_opt [options] [command]\n"); log("\n"); log("This command uses temporal induction to check circuit equivalence before and\n"); - log("after an optimization pass.\n"); + log("after an optimization pass.\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); @@ -50,6 +50,9 @@ struct EquivOptPass:public ScriptPass log(" -multiclock\n"); log(" run clk2fflogic before equivalence checking.\n"); log("\n"); + log(" -async2sync\n"); + log(" run async2sync before equivalence checking.\n"); + log("\n"); log(" -undef\n"); log(" enable modelling of undef states during equiv_induct.\n"); log("\n"); @@ -59,7 +62,7 @@ struct EquivOptPass:public ScriptPass } std::string command, techmap_opts; - bool assert, undef, multiclock; + bool assert, undef, multiclock, async2sync; void clear_flags() YS_OVERRIDE { @@ -68,6 +71,7 @@ struct EquivOptPass:public ScriptPass assert = false; undef = false; multiclock = false; + async2sync = false; } void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE @@ -101,6 +105,10 @@ struct EquivOptPass:public ScriptPass multiclock = true; continue; } + if (args[argidx] == "-async2sync") { + async2sync = true; + continue; + } break; } @@ -120,6 +128,9 @@ struct EquivOptPass:public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (async2sync && multiclock) + log_cmd_error("The '-async2sync' and '-multiclock' options are mutually exclusive!\n"); + log_header(design, "Executing EQUIV_OPT pass.\n"); log_push(); @@ -157,8 +168,8 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); - if (!multiclock || help_mode) - run("async2sync", "(only without -multiclock)"); + if (async2sync || help_mode) + run("async2sync", " (only with -async2sync)"); run("equiv_make gold gate equiv"); if (help_mode) run("equiv_induct [-undef] equiv"); |