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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-02 12:35:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-02 12:35:45 -0700 |
| commit | 35fd9b04731d3bc944e1471b96668ef0cf7b51f1 (patch) | |
| tree | c92e962f36702b99f1934999d9656bb9a7c1a1b2 /passes | |
| parent | 69f4c039ce615c6a6c788e7b0da53e37467d32f6 (diff) | |
| parent | 8455d1f4ffb942c802b65e20748e54a123e08df0 (diff) | |
| download | yosys-35fd9b04731d3bc944e1471b96668ef0cf7b51f1.tar.gz yosys-35fd9b04731d3bc944e1471b96668ef0cf7b51f1.tar.bz2 yosys-35fd9b04731d3bc944e1471b96668ef0cf7b51f1.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/memory/memory_dff.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 5215cce44..32b97f27a 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -17,6 +17,7 @@ * */ +#include <algorithm> #include "kernel/yosys.h" #include "kernel/sigtools.h" @@ -183,12 +184,12 @@ struct MemoryDffWorker if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)) { RTLIL::SigSpec en; - RTLIL::SigSpec check_q; + std::vector<RTLIL::SigSpec> check_q; do { bool enable_invert = mux_cells_a.count(sig_data) != 0; Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); + check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"))); sig_data = sigmap(mux->getPort("\\Y")); en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); @@ -197,7 +198,8 @@ struct MemoryDffWorker if (sigbit_users_count[bit] > 1) goto skip_ff_after_read_merging; - if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q) + if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && + std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; })) { disconnect_dff(sig_data); cell->setPort("\\CLK", clk_data); |