Merge remote-tracking branch 'origin/master' into xaig_dff

7 files changed, 87 insertions, 11 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 5535ce418..ae7d28236 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -12,6 +12,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
     - Added "synth -abc9" (experimental)
+    - Added "script -scriptwire
 
 
 Yosys 0.8 .. Yosys 0.8-dev
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d3fd91473..951d9c66f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
     to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
     global state.. its a mess) */
 [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
+	if (!strcmp(yytext, "default"))
+		return TOK_DEFAULT;
 	frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 	return TOK_SVA_LABEL;
 }
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 94d6d675f..f95c0127b 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -1254,24 +1254,55 @@ struct HistoryPass : public Pass {
 #endif
 
 struct ScriptCmdPass : public Pass {
-	ScriptCmdPass() : Pass("script", "execute commands from script file") { }
+	ScriptCmdPass() : Pass("script", "execute commands from file or wire") { }
 	void help() YS_OVERRIDE {
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    script <filename> [<from_label>:<to_label>]\n");
+		log("    script -scriptwire [selection]\n");
 		log("\n");
-		log("This command executes the yosys commands in the specified file.\n");
+		log("This command executes the yosys commands in the specified file (default\n");
+		log("behaviour), or commands embedded in the constant text value connected to the\n");
+		log("selected wires.\n");
 		log("\n");
-		log("The 2nd argument can be used to only execute the section of the\n");
-		log("file between the specified labels. An empty from label is synonymous\n");
-		log("for the beginning of the file and an empty to label is synonymous\n");
-		log("for the end of the file.\n");
+		log("In the default (file) case, the 2nd argument can be used to only execute the\n");
+		log("section of the file between the specified labels. An empty from label is\n");
+		log("synonymous with the beginning of the file and an empty to label is synonymous\n");
+		log("with the end of the file.\n");
 		log("\n");
 		log("If only one label is specified (without ':') then only the block\n");
 		log("marked with that label (until the next label) is executed.\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
-		if (args.size() < 2)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		bool scriptwire = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-scriptwire") {
+				scriptwire = true;
+				continue;
+			}
+			break;
+		}
+		if (scriptwire) {
+			extra_args(args, argidx, design);
+
+			for (auto mod : design->selected_modules())
+				for (auto &c : mod->connections()) {
+					if (!c.first.is_wire())
+						continue;
+					auto w = c.first.as_wire();
+					if (!mod->selected(w))
+						continue;
+					if (!c.second.is_fully_const())
+						log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w));
+					auto v = c.second.as_const();
+					Pass::call_on_module(design, mod, v.decode_string());
+				}
+		}
+		else if (args.size() < 2)
 			log_cmd_error("Missing script file.\n");
 		else if (args.size() == 2)
 			run_frontend(args[1], "script", design);
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 5215cce44..32b97f27a 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -17,6 +17,7 @@
  *
  */
 
+#include <algorithm>
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 
@@ -183,12 +184,12 @@ struct MemoryDffWorker
 		if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
 		{
 			RTLIL::SigSpec en;
-			RTLIL::SigSpec check_q;
+			std::vector<RTLIL::SigSpec> check_q;
 
 			do {
 				bool enable_invert = mux_cells_a.count(sig_data) != 0;
 				Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
-				check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
+				check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
 				sig_data = sigmap(mux->getPort("\\Y"));
 				en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
 			} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
@@ -197,7 +198,8 @@ struct MemoryDffWorker
 				if (sigbit_users_count[bit] > 1)
 					goto skip_ff_after_read_merging;
 
-			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
+			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) &&
+					std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
 			{
 				disconnect_dff(sig_data);
 				cell->setPort("\\CLK", clk_data);
diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v
new file mode 100644
index 000000000..4f2e7e1cd
--- /dev/null
+++ b/tests/memories/read_two_mux.v
@@ -0,0 +1,16 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-no-rd-clk
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+(* keep *) reg dummy;
+
+always @(posedge clk) begin
+	rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata;
+	if (we)
+		bram[addr] <= wdata;
+end
+
+endmodule
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 76acaa9cd..8d1a8b413 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read clock."; false; }
 	fi
+	if grep -q expect-no-rd-clk $f; then
+		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Expected no read clock."; false; }
+	fi
 	echo " ok."
 done
 
diff --git a/tests/various/script.ys b/tests/various/script.ys
new file mode 100644
index 000000000..66b7b5caa
--- /dev/null
+++ b/tests/various/script.ys
@@ -0,0 +1,20 @@
+read_verilog -formal <<EOT
+    module top;
+        foo bar();
+        foo asdf();
+        winnie the_pooh();
+
+        wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo";
+        wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie";
+    endmodule
+
+    module other;
+        wire [1023:0] _DELETE = "cd; delete c:bar";
+    endmodule
+EOT
+
+script -scriptwire w:_RUNME*
+
+select w:_DELETE
+script -scriptwire
+select -assert-count 1 t:foo