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authorClifford Wolf <clifford@clifford.at>2017-09-15 21:28:16 +0200
committerClifford Wolf <clifford@clifford.at>2017-09-15 21:28:16 +0200
commit5c4ea1366f8fe784f0a51b98a9d812a2e2d1b163 (patch)
tree38e04d04542ab46fc82177175af0e5798abce2d0 /passes/techmap
parent76c11d74546cc5521ffd10100db9141f22bb65db (diff)
parentce78717e3601012e95cf786b87b281e55a3a8391 (diff)
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Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/extract_reduce.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index 114015c23..54e45f836 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -160,7 +160,7 @@ struct ExtractReducePass : public Pass
if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)
{
Cell* cell_a = sig_to_driver[a[0]];
- if (((cell_a->type == "$_AND_" && gt == GateType::And) ||
+ if (cell_a && ((cell_a->type == "$_AND_" && gt == GateType::And) ||
(cell_a->type == "$_OR_" && gt == GateType::Or) ||
(cell_a->type == "$_XOR_" && gt == GateType::Xor)))
{
@@ -177,7 +177,7 @@ struct ExtractReducePass : public Pass
if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)
{
Cell* cell_b = sig_to_driver[b[0]];
- if (((cell_b->type == "$_AND_" && gt == GateType::And) ||
+ if (cell_b && ((cell_b->type == "$_AND_" && gt == GateType::And) ||
(cell_b->type == "$_OR_" && gt == GateType::Or) ||
(cell_b->type == "$_XOR_" && gt == GateType::Xor)))
{