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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 19:09:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 19:09:45 +0200 |
| commit | 6fe48cf41ef0b0158879add600c7a426a5c4a762 (patch) | |
| tree | c9de66f5fe0848219a23492e89d3ff11bd6b63ed /passes | |
| parent | 2a0f577f839bc43a5045ddf5a2b580bba8cabeab (diff) | |
| download | yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.tar.gz yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.tar.bz2 yosys-6fe48cf41ef0b0158879add600c7a426a5c4a762.zip | |
equiv_purge bugfix, using SigChunk in Yosys namespace
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/equiv/equiv_miter.cc | 2 | ||||
| -rw-r--r-- | passes/equiv/equiv_purge.cc | 5 | ||||
| -rw-r--r-- | passes/techmap/extract.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
4 files changed, 6 insertions, 5 deletions
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 34318dec2..982176c44 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -156,7 +156,7 @@ struct EquivMiterWorker struct RewriteSigSpecWorker { RTLIL::Module * mod; void operator()(SigSpec &sig) { - vector<RTLIL::SigChunk> chunks = sig.chunks(); + vector<SigChunk> chunks = sig.chunks(); for (auto &c : chunks) if (c.wire != NULL) c.wire = mod->wires_.at(c.wire->name); diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index e14ffe31c..f4141ad4d 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -162,8 +162,9 @@ struct EquivPurgeWorker srcsig.sort_and_unify(); - for (SigSpec sig : srcsig.chunks()) - rewrite_sigmap.add(sig, make_input(sig)); + for (SigChunk chunk : srcsig.chunks()) + if (chunk.wire != nullptr) + rewrite_sigmap.add(chunk, make_input(chunk)); for (auto cell : module->cells()) if (cell->type == "$equiv") diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 68a7fc1f6..d9ec4bc6a 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -737,7 +737,7 @@ struct ExtractPass : public Pass { RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; for (auto &conn : cell->connections()) { - std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second); + std::vector<SigChunk> chunks = sigmap(conn.second); for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires_.at(chunk.wire->name); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 592710eda..19b2bda9c 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -49,7 +49,7 @@ void apply_prefix(std::string prefix, std::string &id) void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) { - std::vector<RTLIL::SigChunk> chunks = sig; + vector<SigChunk> chunks = sig; for (auto &chunk : chunks) if (chunk.wire != NULL) { std::string wire_name = chunk.wire->name.str(); |