diff options
| author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 18:34:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 18:36:02 +0200 |
| commit | fa535c0b0041621d0128087cd0236cfd5eb36e48 (patch) | |
| tree | be7017c8cbd351674b56ae7206e5e95a1d6f4c63 /passes/sat | |
| parent | e4c5ee9b893bf7dd2b9102934ebb1f1a6f0671a9 (diff) | |
| download | yosys-fa535c0b0041621d0128087cd0236cfd5eb36e48.tar.gz yosys-fa535c0b0041621d0128087cd0236cfd5eb36e48.tar.bz2 yosys-fa535c0b0041621d0128087cd0236cfd5eb36e48.zip | |
Some minor build fixes for Visual C
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 2934daadc..ecdc8621c 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -93,8 +93,17 @@ struct Clk2fflogicPass : public Pass { log_signal(clk), log_signal(sig_d), log_signal(sig_q)); module->remove(cell); - SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk}, - clkpol ? SigSpec({State::S0, State::S1}) : SigSpec({State::S1, State::S0})); + SigSpec clock_edge_pattern; + + if (clkpol) { + clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append_bit(State::S1); + } else { + clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append_bit(State::S0); + } + + SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk}, clock_edge_pattern); Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q)); |