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author | whitequark <whitequark@whitequark.org> | 2020-06-19 06:15:33 +0000 |
---|---|---|
committer | GitHub <noreply@github.com> | 2020-06-19 06:15:33 +0000 |
commit | ede4b10da8fdbdcff900b93c6c723516901483ff (patch) | |
tree | d949c995f56d6c07dfe7d18ca46547a3296079b6 /passes/sat | |
parent | bcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff) | |
parent | 60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff) | |
download | yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.gz yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.bz2 yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.zip |
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'passes/sat')
-rw-r--r-- | passes/sat/assertpmux.cc | 4 | ||||
-rw-r--r-- | passes/sat/async2sync.cc | 4 | ||||
-rw-r--r-- | passes/sat/clk2fflogic.cc | 4 | ||||
-rw-r--r-- | passes/sat/cutpoint.cc | 4 | ||||
-rw-r--r-- | passes/sat/eval.cc | 4 | ||||
-rw-r--r-- | passes/sat/expose.cc | 4 | ||||
-rw-r--r-- | passes/sat/fmcombine.cc | 4 | ||||
-rw-r--r-- | passes/sat/fminit.cc | 4 | ||||
-rw-r--r-- | passes/sat/freduce.cc | 4 | ||||
-rw-r--r-- | passes/sat/miter.cc | 4 | ||||
-rw-r--r-- | passes/sat/mutate.cc | 4 | ||||
-rw-r--r-- | passes/sat/qbfsat.cc | 4 | ||||
-rw-r--r-- | passes/sat/sat.cc | 4 | ||||
-rw-r--r-- | passes/sat/sim.cc | 4 | ||||
-rw-r--r-- | passes/sat/supercover.cc | 4 |
15 files changed, 30 insertions, 30 deletions
diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 5bf2296ab..e9a10465e 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -181,7 +181,7 @@ struct AssertpmuxWorker struct AssertpmuxPass : public Pass { AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -199,7 +199,7 @@ struct AssertpmuxPass : public Pass { log(" additional constraint and check the $pmux condition always.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { bool flag_noinit = false; bool flag_always = false; diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index e344e2b5b..6fc480925 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Async2syncPass : public Pass { Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -42,7 +42,7 @@ struct Async2syncPass : public Pass { log("Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { // bool flag_noinit = false; diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 1e155e52c..e5c5d0486 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Clk2fflogicPass : public Pass { Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct Clk2fflogicPass : public Pass { log("multiple clocks.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { // bool flag_noinit = false; diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 27dc10523..6fc267d51 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct CutpointPass : public Pass { CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -38,7 +38,7 @@ struct CutpointPass : public Pass { log(" $anyseq cell and drive the cutpoint net from that\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { bool flag_undef = false; diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index f910ea80d..085e7c5b8 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -359,7 +359,7 @@ struct VlogHammerReporter struct EvalPass : public Pass { EvalPass() : Pass("eval", "evaluate the circuit given an input") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -382,7 +382,7 @@ struct EvalPass : public Pass { log(" then all output ports of the current module are used.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { std::vector<std::pair<std::string, std::string>> sets; std::vector<std::string> shows, tables; diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 80ab82cd5..5fe7efc34 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -217,7 +217,7 @@ RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width struct ExposePass : public Pass { ExposePass() : Pass("expose", "convert internal signals to module ports") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -254,7 +254,7 @@ struct ExposePass : public Pass { log(" designator for the exposed signal.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { bool flag_shared = false; bool flag_evert = false; diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 5066485aa..5694a7473 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -235,7 +235,7 @@ struct FmcombineWorker struct FmcombinePass : public Pass { FmcombinePass() : Pass("fmcombine", "combine two instances of a cell into one") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -272,7 +272,7 @@ struct FmcombinePass : public Pass { log("If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { opts_t opts; Module *module = nullptr; diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 555a28dc6..c72e62548 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct FminitPass : public Pass { FminitPass() : Pass("fminit", "set init values/sequences for formal") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -47,7 +47,7 @@ struct FminitPass : public Pass { log(" Set clock for init sequences\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { vector<pair<string, vector<string>>> initdata; vector<pair<string, string>> setdata; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 5dfd7bd3f..762edfdfb 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -760,7 +760,7 @@ struct FreduceWorker struct FreducePass : public Pass { FreducePass() : Pass("freduce", "perform functional reduction") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -791,7 +791,7 @@ struct FreducePass : public Pass { log("circuit that is analyzed.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { reduce_counter = 0; reduce_stop_at = 0; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index aeece9b94..fe4a819f3 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -354,7 +354,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL struct MiterPass : public Pass { MiterPass() : Pass("miter", "automatically create a miter circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -398,7 +398,7 @@ struct MiterPass : public Pass { log(" call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { if (args.size() > 1 && args[1] == "-equiv") { create_miter_equiv(this, args, design); diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index af8ffca9e..15abee73e 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -726,7 +726,7 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one) struct MutatePass : public Pass { MutatePass() : Pass("mutate", "generate or apply design mutations") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -790,7 +790,7 @@ struct MutatePass : public Pass { log(" Ignored. (They are generated by -list for documentation purposes.)\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { mutate_opts_t opts; string filename; diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index d6dbf8ef4..4686e985b 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -623,7 +623,7 @@ void print_qed() struct QbfSatPass : public Pass { QbfSatPass() : Pass("qbfsat", "solve a 2QBF-SAT problem in the circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -690,7 +690,7 @@ struct QbfSatPass : public Pass { log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing QBFSAT pass (solving QBF-SAT problems in the circuit).\n"); QbfSolveOptions opt = parse_args(args); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index e2fe5b846..d7bf125d1 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -893,7 +893,7 @@ void print_qed() struct SatPass : public Pass { SatPass() : Pass("sat", "solve a SAT problem in the circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1060,7 +1060,7 @@ struct SatPass : public Pass { log(" Like -falsify but do not return an error for timeouts.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { std::vector<std::pair<std::string, std::string>> sets, sets_init, prove, prove_x; std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 03ca42cf3..1ab082b09 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -751,7 +751,7 @@ struct SimWorker : SimShared struct SimPass : public Pass { SimPass() : Pass("sim", "simulate the circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -793,7 +793,7 @@ struct SimPass : public Pass { log(" enable debug output\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { SimWorker worker; int numcycles = 20; diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index ba44f02d8..aacc044fb 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct SupercoverPass : public Pass { SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct SupercoverPass : public Pass { log("checking for a hi signal level and one checking for lo level.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { // bool flag_noinit = false; |