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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 12:41:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 12:41:24 -0700 |
| commit | ea54b5ea61ee242e1dfa7f257a10095f267b8171 (patch) | |
| tree | 5dfb2f9a6834bfcd1ce1307b24ee4575679b1d60 /passes/sat | |
| parent | cfc181cba9837f42d9faa8ba9dbffbcede0ca84b (diff) | |
| download | yosys-ea54b5ea61ee242e1dfa7f257a10095f267b8171.tar.gz yosys-ea54b5ea61ee242e1dfa7f257a10095f267b8171.tar.bz2 yosys-ea54b5ea61ee242e1dfa7f257a10095f267b8171.zip | |
Revert "Be mindful that sigmap(wire) could have dupes when checking \init"
This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1.
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sat.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 93a4f225e..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -265,18 +265,15 @@ struct SatHelper RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); log_assert(lhs.size() == rhs.size()); - dict<RTLIL::SigBit,SigBit> seen_init; RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); i--; } - else - seen_init[bit] = rhs[i]; } if (removed_bits.size()) |