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authorclairexen <claire@symbioticeda.com>2020-07-02 17:43:48 +0200
committerGitHub <noreply@github.com>2020-07-02 17:43:48 +0200
commitd3422f8a5e77a472d900f5cdd4066b848839a68f (patch)
tree065fcc6091a8eebe35ab5511ae07622d2b52eb68 /passes/sat
parent5dbf91847a79b5e2639078c1cbdbfadcbe439ea0 (diff)
parent7c91f13f51c6c93dbece0eed91977241b7c346df (diff)
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Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff
fmcombine: use the master ff cell type list
Diffstat (limited to 'passes/sat')
-rw-r--r--passes/sat/fmcombine.cc3
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index 5694a7473..cb49edac3 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -114,8 +114,7 @@ struct FmcombineWorker
Cell *gold = import_prim_cell(cell, "_gold");
Cell *gate = import_prim_cell(cell, "_gate");
if (opts.initeq) {
- if (cell->type.in(ID($ff), ID($dff), ID($dffe),
- ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr))) {
+ if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
SigSpec gold_q = gold->getPort(ID::Q);
SigSpec gate_q = gate->getPort(ID::Q);
SigSpec en = module->Initstate(NEW_ID);