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| author | David Shah <dave@ds0.me> | 2020-04-21 08:58:52 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-04-21 08:58:52 +0100 |
| commit | abf81c76396d674833d1dce3f3f75a43f76e2a1f (patch) | |
| tree | 8783842cec0215c2d063ef3647273826d05b0905 /passes/sat | |
| parent | c98cde88427aedacbcaf66d915912377ccb0cb01 (diff) | |
| download | yosys-abf81c76396d674833d1dce3f3f75a43f76e2a1f.tar.gz yosys-abf81c76396d674833d1dce3f3f75a43f76e2a1f.tar.bz2 yosys-abf81c76396d674833d1dce3f3f75a43f76e2a1f.zip | |
sim: Fix handling of constant-connected cell inputs at startup
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 59bf5a712..03ca42cf3 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -128,8 +128,12 @@ struct SimInstance for (auto &port : cell->connections()) { if (cell->input(port.first)) - for (auto bit : sigmap(port.second)) + for (auto bit : sigmap(port.second)) { upd_cells[bit].insert(cell); + // Make sure cell inputs connected to constants are updated in the first cycle + if (bit.wire == nullptr) + dirty_bits.insert(bit); + } } if (cell->type.in(ID($dff))) { |