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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-03-30 16:25:30 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-03-30 16:25:30 +0000 |
| commit | 9f265dfd3f9ae087fa22ffd809c00625fc6e2c65 (patch) | |
| tree | 0b45caf4f02bfddece86674fd74218f4d1293961 /passes/sat | |
| parent | 9a0cdc38356500de386bc274034195c54c3c91e2 (diff) | |
| download | yosys-9f265dfd3f9ae087fa22ffd809c00625fc6e2c65.tar.gz yosys-9f265dfd3f9ae087fa22ffd809c00625fc6e2c65.tar.bz2 yosys-9f265dfd3f9ae087fa22ffd809c00625fc6e2c65.zip | |
Further clean up `passes/sat/freduce.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/freduce.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 7dfc1765f..54016e528 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -828,9 +828,8 @@ struct FreducePass : public Pass { extra_args(args, argidx, design); int bitcount = 0; - for (auto module : design->modules()) { - if (design->selected(module)) - bitcount += FreduceWorker(design, module).run(); + for (auto module : design->selected_modules()) { + bitcount += FreduceWorker(design, module).run(); } log("Rewired a total of %d signal bits.\n", bitcount); |