kernel: big fat patch to use more ID::*, otherwise ID(*)

12 files changed, 272 insertions, 272 deletions

diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index b4adb1ab3..5bf2296ab 100644
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -52,10 +52,10 @@ struct AssertpmuxWorker
 
 		for (auto cell : module->cells())
 		{
-			if (cell->type.in("$mux", "$pmux"))
+			if (cell->type.in(ID($mux), ID($pmux)))
 			{
-				int width = cell->getParam("\\WIDTH").as_int();
-				int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1;
+				int width = cell->getParam(ID::WIDTH).as_int();
+				int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
 
 				SigSpec sig_a = sigmap(cell->getPort(ID::A));
 				SigSpec sig_b = sigmap(cell->getPort(ID::B));
@@ -148,7 +148,7 @@ struct AssertpmuxWorker
 	{
 		log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux));
 
-		int swidth = pmux->getParam("\\S_WIDTH").as_int();
+		int swidth = pmux->getParam(ID::S_WIDTH).as_int();
 		int cntbits = ceil_log2(swidth+1);
 
 		SigSpec sel = pmux->getPort(ID::S);
@@ -227,7 +227,7 @@ struct AssertpmuxPass : public Pass {
 			vector<Cell*> pmux_cells;
 
 			for (auto cell : module->selected_cells())
-				if (cell->type == "$pmux")
+				if (cell->type == ID($pmux))
 					pmux_cells.push_back(cell);
 
 			for (auto cell : pmux_cells)
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index 740248545..e344e2b5b 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -66,9 +66,9 @@ struct Async2syncPass : public Pass {
 			pool<SigBit> del_initbits;
 
 			for (auto wire : module->wires())
-				if (wire->attributes.count("\\init") > 0)
+				if (wire->attributes.count(ID::init) > 0)
 				{
-					Const initval = wire->attributes.at("\\init");
+					Const initval = wire->attributes.at(ID::init);
 					SigSpec initsig = sigmap(wire);
 
 					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -78,16 +78,16 @@ struct Async2syncPass : public Pass {
 
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				if (cell->type.in("$adff"))
+				if (cell->type.in(ID($adff)))
 				{
-					// bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
-					bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool();
-					Const arst_val = cell->parameters["\\ARST_VALUE"];
+					// bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
+					bool arst_pol = cell->parameters[ID::ARST_POLARITY].as_bool();
+					Const arst_val = cell->parameters[ID::ARST_VALUE];
 
-					// SigSpec sig_clk = cell->getPort("\\CLK");
-					SigSpec sig_arst = cell->getPort("\\ARST");
-					SigSpec sig_d = cell->getPort("\\D");
-					SigSpec sig_q = cell->getPort("\\Q");
+					// SigSpec sig_clk = cell->getPort(ID::CLK);
+					SigSpec sig_arst = cell->getPort(ID::ARST);
+					SigSpec sig_d = cell->getPort(ID::D);
+					SigSpec sig_q = cell->getPort(ID::Q);
 
 					log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
 							log_id(module), log_id(cell), log_id(cell->type),
@@ -102,7 +102,7 @@ struct Async2syncPass : public Pass {
 
 					Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
 					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
-					new_q->attributes["\\init"] = init_val;
+					new_q->attributes[ID::init] = init_val;
 
 					if (arst_pol) {
 						module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
@@ -112,26 +112,26 @@ struct Async2syncPass : public Pass {
 						module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
 					}
 
-					cell->setPort("\\D", new_d);
-					cell->setPort("\\Q", new_q);
-					cell->unsetPort("\\ARST");
-					cell->unsetParam("\\ARST_POLARITY");
-					cell->unsetParam("\\ARST_VALUE");
-					cell->type = "$dff";
+					cell->setPort(ID::D, new_d);
+					cell->setPort(ID::Q, new_q);
+					cell->unsetPort(ID::ARST);
+					cell->unsetParam(ID::ARST_POLARITY);
+					cell->unsetParam(ID::ARST_VALUE);
+					cell->type = ID($dff);
 					continue;
 				}
 
-				if (cell->type.in("$dffsr"))
+				if (cell->type.in(ID($dffsr)))
 				{
-					// bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
-					bool set_pol = cell->parameters["\\SET_POLARITY"].as_bool();
-					bool clr_pol = cell->parameters["\\CLR_POLARITY"].as_bool();
+					// bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
+					bool set_pol = cell->parameters[ID::SET_POLARITY].as_bool();
+					bool clr_pol = cell->parameters[ID::CLR_POLARITY].as_bool();
 
-					// SigSpec sig_clk = cell->getPort("\\CLK");
-					SigSpec sig_set = cell->getPort("\\SET");
-					SigSpec sig_clr = cell->getPort("\\CLR");
-					SigSpec sig_d = cell->getPort("\\D");
-					SigSpec sig_q = cell->getPort("\\Q");
+					// SigSpec sig_clk = cell->getPort(ID::CLK);
+					SigSpec sig_set = cell->getPort(ID::SET);
+					SigSpec sig_clr = cell->getPort(ID::CLR);
+					SigSpec sig_d = cell->getPort(ID::D);
+					SigSpec sig_q = cell->getPort(ID::Q);
 
 					log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
 							log_id(module), log_id(cell), log_id(cell->type),
@@ -146,7 +146,7 @@ struct Async2syncPass : public Pass {
 
 					Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
 					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
-					new_q->attributes["\\init"] = init_val;
+					new_q->attributes[ID::init] = init_val;
 
 					if (!set_pol)
 						sig_set = module->Not(NEW_ID, sig_set);
@@ -160,23 +160,23 @@ struct Async2syncPass : public Pass {
 					tmp = module->Or(NEW_ID, new_q, sig_set);
 					module->addAnd(NEW_ID, tmp, sig_clr, sig_q);
 
-					cell->setPort("\\D", new_d);
-					cell->setPort("\\Q", new_q);
-					cell->unsetPort("\\SET");
-					cell->unsetPort("\\CLR");
-					cell->unsetParam("\\SET_POLARITY");
-					cell->unsetParam("\\CLR_POLARITY");
-					cell->type = "$dff";
+					cell->setPort(ID::D, new_d);
+					cell->setPort(ID::Q, new_q);
+					cell->unsetPort(ID::SET);
+					cell->unsetPort(ID::CLR);
+					cell->unsetParam(ID::SET_POLARITY);
+					cell->unsetParam(ID::CLR_POLARITY);
+					cell->type = ID($dff);
 					continue;
 				}
 
-				if (cell->type.in("$dlatch"))
+				if (cell->type.in(ID($dlatch)))
 				{
-					bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool();
+					bool en_pol = cell->parameters[ID::EN_POLARITY].as_bool();
 
-					SigSpec sig_en = cell->getPort("\\EN");
-					SigSpec sig_d = cell->getPort("\\D");
-					SigSpec sig_q = cell->getPort("\\Q");
+					SigSpec sig_en = cell->getPort(ID::EN);
+					SigSpec sig_d = cell->getPort(ID::D);
+					SigSpec sig_q = cell->getPort(ID::Q);
 
 					log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
 							log_id(module), log_id(cell), log_id(cell->type),
@@ -190,7 +190,7 @@ struct Async2syncPass : public Pass {
 					}
 
 					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
-					new_q->attributes["\\init"] = init_val;
+					new_q->attributes[ID::init] = init_val;
 
 					if (en_pol) {
 						module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
@@ -198,20 +198,20 @@ struct Async2syncPass : public Pass {
 						module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
 					}
 
-					cell->setPort("\\D", sig_q);
-					cell->setPort("\\Q", new_q);
-					cell->unsetPort("\\EN");
-					cell->unsetParam("\\EN_POLARITY");
-					cell->type = "$ff";
+					cell->setPort(ID::D, sig_q);
+					cell->setPort(ID::Q, new_q);
+					cell->unsetPort(ID::EN);
+					cell->unsetParam(ID::EN_POLARITY);
+					cell->type = ID($ff);
 					continue;
 				}
 			}
 
 			for (auto wire : module->wires())
-				if (wire->attributes.count("\\init") > 0)
+				if (wire->attributes.count(ID::init) > 0)
 				{
 					bool delete_initattr = true;
-					Const initval = wire->attributes.at("\\init");
+					Const initval = wire->attributes.at(ID::init);
 					SigSpec initsig = sigmap(wire);
 
 					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -221,9 +221,9 @@ struct Async2syncPass : public Pass {
 							delete_initattr = false;
 
 					if (delete_initattr)
-						wire->attributes.erase("\\init");
+						wire->attributes.erase(ID::init);
 					else
-						wire->attributes.at("\\init") = initval;
+						wire->attributes.at(ID::init) = initval;
 				}
 		}
 	}
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index cc16a767c..1e155e52c 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -60,9 +60,9 @@ struct Clk2fflogicPass : public Pass {
 			pool<SigBit> del_initbits;
 
 			for (auto wire : module->wires())
-				if (wire->attributes.count("\\init") > 0)
+				if (wire->attributes.count(ID::init) > 0)
 				{
-					Const initval = wire->attributes.at("\\init");
+					Const initval = wire->attributes.at(ID::init);
 					SigSpec initsig = sigmap(wire);
 
 					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -72,26 +72,26 @@ struct Clk2fflogicPass : public Pass {
 
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				if (cell->type.in("$mem"))
+				if (cell->type.in(ID($mem)))
 				{
-					int abits = cell->getParam("\\ABITS").as_int();
-					int width = cell->getParam("\\WIDTH").as_int();
-					int rd_ports = cell->getParam("\\RD_PORTS").as_int();
-					int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+					int abits = cell->getParam(ID::ABITS).as_int();
+					int width = cell->getParam(ID::WIDTH).as_int();
+					int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+					int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
 
 					for (int i = 0; i < rd_ports; i++) {
-						if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+						if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
 							log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
 									"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module));
 					}
 
-					Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE");
-					Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY");
+					Const wr_clk_en_param = cell->getParam(ID::WR_CLK_ENABLE);
+					Const wr_clk_pol_param = cell->getParam(ID::WR_CLK_POLARITY);
 
-					SigSpec wr_clk_port = cell->getPort("\\WR_CLK");
-					SigSpec wr_en_port = cell->getPort("\\WR_EN");
-					SigSpec wr_addr_port = cell->getPort("\\WR_ADDR");
-					SigSpec wr_data_port = cell->getPort("\\WR_DATA");
+					SigSpec wr_clk_port = cell->getPort(ID::WR_CLK);
+					SigSpec wr_en_port = cell->getPort(ID::WR_EN);
+					SigSpec wr_addr_port = cell->getPort(ID::WR_ADDR);
+					SigSpec wr_data_port = cell->getPort(ID::WR_DATA);
 
 					for (int wport = 0; wport < wr_ports; wport++)
 					{
@@ -111,7 +111,7 @@ struct Clk2fflogicPass : public Pass {
 								log_signal(addr), log_signal(data));
 
 						Wire *past_clk = module->addWire(NEW_ID);
-						past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+						past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
 						module->addFf(NEW_ID, clk, past_clk);
 
 						SigSpec clock_edge_pattern;
@@ -144,22 +144,22 @@ struct Clk2fflogicPass : public Pass {
 						wr_clk_pol_param[wport] = State::S0;
 					}
 
-					cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param);
-					cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param);
+					cell->setParam(ID::WR_CLK_ENABLE, wr_clk_en_param);
+					cell->setParam(ID::WR_CLK_POLARITY, wr_clk_pol_param);
 
-					cell->setPort("\\WR_CLK", wr_clk_port);
-					cell->setPort("\\WR_EN", wr_en_port);
-					cell->setPort("\\WR_ADDR", wr_addr_port);
-					cell->setPort("\\WR_DATA", wr_data_port);
+					cell->setPort(ID::WR_CLK, wr_clk_port);
+					cell->setPort(ID::WR_EN, wr_en_port);
+					cell->setPort(ID::WR_ADDR, wr_addr_port);
+					cell->setPort(ID::WR_DATA, wr_data_port);
 				}
 
-				if (cell->type.in("$dlatch", "$dlatchsr"))
+				if (cell->type.in(ID($dlatch), ID($dlatchsr)))
 				{
-					bool enpol = cell->parameters["\\EN_POLARITY"].as_bool();
+					bool enpol = cell->parameters[ID::EN_POLARITY].as_bool();
 
-					SigSpec sig_en = cell->getPort("\\EN");
-					SigSpec sig_d = cell->getPort("\\D");
-					SigSpec sig_q = cell->getPort("\\Q");
+					SigSpec sig_en = cell->getPort(ID::EN);
+					SigSpec sig_d = cell->getPort(ID::D);
+					SigSpec sig_q = cell->getPort(ID::Q);
 
 					log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
 							log_id(module), log_id(cell), log_id(cell->type),
@@ -168,7 +168,7 @@ struct Clk2fflogicPass : public Pass {
 					Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
 					module->addFf(NEW_ID, sig_q, past_q);
 
-					if (cell->type == "$dlatch")
+					if (cell->type == ID($dlatch))
 					{
 						if (enpol)
 							module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
@@ -183,13 +183,13 @@ struct Clk2fflogicPass : public Pass {
 						else
 							t = module->Mux(NEW_ID, sig_d, past_q, sig_en);
 
-						SigSpec s = cell->getPort("\\SET");
-						if (!cell->parameters["\\SET_POLARITY"].as_bool())
+						SigSpec s = cell->getPort(ID::SET);
+						if (!cell->parameters[ID::SET_POLARITY].as_bool())
 							s = module->Not(NEW_ID, s);
 						t = module->Or(NEW_ID, t, s);
 
-						SigSpec c = cell->getPort("\\CLR");
-						if (cell->parameters["\\CLR_POLARITY"].as_bool())
+						SigSpec c = cell->getPort(ID::CLR);
+						if (cell->parameters[ID::CLR_POLARITY].as_bool())
 							c = module->Not(NEW_ID, c);
 						module->addAnd(NEW_ID, t, c, sig_q);
 					}
@@ -208,13 +208,13 @@ struct Clk2fflogicPass : public Pass {
 					}
 
 					if (assign_initval)
-						past_q->attributes["\\init"] = initval;
+						past_q->attributes[ID::init] = initval;
 
 					module->remove(cell);
 					continue;
 				}
 
-				bool word_dff = cell->type.in("$dff", "$adff", "$dffsr");
+				bool word_dff = cell->type.in(ID($dff), ID($adff), ID($dffsr));
 				if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_),
 						ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
 						ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
@@ -224,8 +224,8 @@ struct Clk2fflogicPass : public Pass {
 					bool clkpol;
 					SigSpec clk;
 					if (word_dff) {
-						clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
-						clk = cell->getPort("\\CLK");
+						clkpol = cell->parameters[ID::CLK_POLARITY].as_bool();
+						clk = cell->getPort(ID::CLK);
 					}
 					else {
 						if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_),
@@ -236,19 +236,19 @@ struct Clk2fflogicPass : public Pass {
 									ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
 							clkpol = cell->type[8] == 'P';
 						else log_abort();
-						clk = cell->getPort("\\C");
+						clk = cell->getPort(ID::C);
 					}
 
 					Wire *past_clk = module->addWire(NEW_ID);
-					past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+					past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
 
 					if (word_dff)
 						module->addFf(NEW_ID, clk, past_clk);
 					else
 						module->addFfGate(NEW_ID, clk, past_clk);
 
-					SigSpec sig_d = cell->getPort("\\D");
-					SigSpec sig_q = cell->getPort("\\Q");
+					SigSpec sig_d = cell->getPort(ID::D);
+					SigSpec sig_q = cell->getPort(ID::Q);
 
 					log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
 							log_id(module), log_id(cell), log_id(cell->type),
@@ -277,20 +277,20 @@ struct Clk2fflogicPass : public Pass {
 						module->addFfGate(NEW_ID, sig_q, past_q);
 					}
 
-					if (cell->type == "$adff")
+					if (cell->type == ID($adff))
 					{
-						SigSpec arst = cell->getPort("\\ARST");
+						SigSpec arst = cell->getPort(ID::ARST);
 						SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
-						Const rstval = cell->parameters["\\ARST_VALUE"];
+						Const rstval = cell->parameters[ID::ARST_VALUE];
 
 						Wire *past_arst = module->addWire(NEW_ID);
 						module->addFf(NEW_ID, arst, past_arst);
-						if (cell->parameters["\\ARST_POLARITY"].as_bool())
+						if (cell->parameters[ID::ARST_POLARITY].as_bool())
 							arst = module->LogicOr(NEW_ID, arst, past_arst);
 						else
 							arst = module->LogicAnd(NEW_ID, arst, past_arst);
 
-						if (cell->parameters["\\ARST_POLARITY"].as_bool())
+						if (cell->parameters[ID::ARST_POLARITY].as_bool())
 							module->addMux(NEW_ID, qval, rstval, arst, sig_q);
 						else
 							module->addMux(NEW_ID, rstval, qval, arst, sig_q);
@@ -299,7 +299,7 @@ struct Clk2fflogicPass : public Pass {
 					if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
 						ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
 					{
-						SigSpec arst = cell->getPort("\\R");
+						SigSpec arst = cell->getPort(ID::R);
 						SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
 						SigBit rstval = (cell->type[8] == '1');
 
@@ -316,16 +316,16 @@ struct Clk2fflogicPass : public Pass {
 							module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q);
 					}
 					else
-					if (cell->type == "$dffsr")
+					if (cell->type == ID($dffsr))
 					{
 						SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
-						SigSpec setval = cell->getPort("\\SET");
-						SigSpec clrval = cell->getPort("\\CLR");
+						SigSpec setval = cell->getPort(ID::SET);
+						SigSpec clrval = cell->getPort(ID::CLR);
 
-						if (!cell->parameters["\\SET_POLARITY"].as_bool())
+						if (!cell->parameters[ID::SET_POLARITY].as_bool())
 							setval = module->Not(NEW_ID, setval);
 
-						if (cell->parameters["\\CLR_POLARITY"].as_bool())
+						if (cell->parameters[ID::CLR_POLARITY].as_bool())
 							clrval = module->Not(NEW_ID, clrval);
 
 						qval = module->Or(NEW_ID, qval, setval);
@@ -337,7 +337,7 @@ struct Clk2fflogicPass : public Pass {
 					{
 						SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
 						SigSpec setval = cell->getPort(ID::S);
-						SigSpec clrval = cell->getPort("\\R");
+						SigSpec clrval = cell->getPort(ID::R);
 
 						if (cell->type[9] != 'P')
 							setval = module->Not(NEW_ID, setval);
@@ -348,7 +348,7 @@ struct Clk2fflogicPass : public Pass {
 						qval = module->OrGate(NEW_ID, qval, setval);
 						module->addAndGate(NEW_ID, qval, clrval, sig_q);
 					}
-					else if (cell->type == "$dff")
+					else if (cell->type == ID($dff))
 					{
 						module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
 					}
@@ -371,8 +371,8 @@ struct Clk2fflogicPass : public Pass {
 					}
 
 					if (assign_initval) {
-						past_d->attributes["\\init"] = initval;
-						past_q->attributes["\\init"] = initval;
+						past_d->attributes[ID::init] = initval;
+						past_q->attributes[ID::init] = initval;
 					}
 
 					module->remove(cell);
@@ -381,10 +381,10 @@ struct Clk2fflogicPass : public Pass {
 			}
 
 			for (auto wire : module->wires())
-				if (wire->attributes.count("\\init") > 0)
+				if (wire->attributes.count(ID::init) > 0)
 				{
 					bool delete_initattr = true;
-					Const initval = wire->attributes.at("\\init");
+					Const initval = wire->attributes.at(ID::init);
 					SigSpec initsig = sigmap(wire);
 
 					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -394,9 +394,9 @@ struct Clk2fflogicPass : public Pass {
 							delete_initattr = false;
 
 					if (delete_initattr)
-						wire->attributes.erase("\\init");
+						wire->attributes.erase(ID::init);
 					else
-						wire->attributes.at("\\init") = initval;
+						wire->attributes.at(ID::init) = initval;
 				}
 		}
 
diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index b4549bc39..26cc69211 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -75,7 +75,7 @@ struct CutpointPass : public Pass {
 			pool<SigBit> cutpoint_bits;
 
 			for (auto cell : module->selected_cells()) {
-				if (cell->type == "$anyseq")
+				if (cell->type == ID($anyseq))
 					continue;
 				log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
 				for (auto &conn : cell->connections()) {
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 148480d55..f910ea80d 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -153,11 +153,11 @@ struct VlogHammerReporter
 
 		ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
 
-		std::vector<int> y_vec = satgen.importDefSigSpec(module->wire("\\y"));
+		std::vector<int> y_vec = satgen.importDefSigSpec(module->wire(ID(y)));
 		std::vector<bool> y_values;
 
 		if (model_undef) {
-			std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire("\\y"));
+			std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire(ID(y)));
 			y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
 		}
 
@@ -268,10 +268,10 @@ struct VlogHammerReporter
 					}
 				}
 
-				if (module->wire("\\y") == nullptr)
+				if (module->wire(ID(y)) == nullptr)
 					log_error("No output wire (y) found in module %s!\n", log_id(module->name));
 
-				RTLIL::SigSpec sig(module->wire("\\y"));
+				RTLIL::SigSpec sig(module->wire(ID(y)));
 				RTLIL::SigSpec undef;
 
 				while (!ce.eval(sig, undef)) {
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 4f0ba44f6..80ab82cd5 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -86,8 +86,8 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
 	SigPool dffsignals;
 
 	for (auto cell : module->cells()) {
-		if (ct.cell_known(cell->type) && cell->hasPort("\\Q"))
-			dffsignals.add(sigmap(cell->getPort("\\Q")));
+		if (ct.cell_known(cell->type) && cell->hasPort(ID::Q))
+			dffsignals.add(sigmap(cell->getPort(ID::Q)));
 	}
 
 	for (auto w : module->wires()) {
@@ -112,11 +112,11 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
 		info.arst_value = RTLIL::State::Sm;
 		info.cell = cell;
 
-		if (info.cell->type == "$dff") {
-			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
-			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
+		if (info.cell->type == ID($dff)) {
+			info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
+			info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
 				bit_info[sig_q.at(i)] = info;
@@ -124,14 +124,14 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
 			continue;
 		}
 
-		if (info.cell->type == "$adff") {
-			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
-			info.bit_arst = sigmap(info.cell->getPort("\\ARST")).as_bit();
-			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
-			info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
-			std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
+		if (info.cell->type == ID($adff)) {
+			info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
+			info.bit_arst = sigmap(info.cell->getPort(ID::ARST)).as_bit();
+			info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
+			info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
+			std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits;
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
 				info.arst_value = arst_value.at(i);
@@ -140,22 +140,22 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
 			continue;
 		}
 
-		if (info.cell->type.in("$_DFF_N_", "$_DFF_P_")) {
-			info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
-			info.clk_polarity = info.cell->type == "$_DFF_P_";
-			info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
-			bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
+		if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
+			info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
+			info.clk_polarity = info.cell->type == ID($_DFF_P_);
+			info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
+			bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
 			continue;
 		}
 
 		if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) {
-			info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
-			info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit();
+			info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
+			info.bit_arst = sigmap(info.cell->getPort(ID::R)).as_bit();
 			info.clk_polarity = info.cell->type[6] == 'P';
 			info.arst_polarity = info.cell->type[7] == 'P';
 			info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
-			info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
-			bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
+			info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
+			bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
 			continue;
 		}
 	}
@@ -526,11 +526,11 @@ struct ExposePass : public Pass {
 
 				for (auto &cell_name : info.cells) {
 					RTLIL::Cell *cell = module->cell(cell_name);
-					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
+					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort(ID::Q)).to_sigbit_vector();
 					for (auto &bit : cell_q_bits)
 						if (wire_bits_set.count(bit))
 							bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
-					cell->setPort("\\Q", cell_q_bits);
+					cell->setPort(ID::Q, cell_q_bits);
 				}
 
 				RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
@@ -558,10 +558,10 @@ struct ExposePass : public Pass {
 				if (info.clk_polarity) {
 					module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
 				} else {
-					RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
-					c->parameters["\\A_SIGNED"] = 0;
-					c->parameters["\\A_WIDTH"] = 1;
-					c->parameters["\\Y_WIDTH"] = 1;
+					RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
+					c->parameters[ID::A_SIGNED] = 0;
+					c->parameters[ID::A_WIDTH] = 1;
+					c->parameters[ID::Y_WIDTH] = 1;
 					c->setPort(ID::A, info.sig_clk);
 					c->setPort(ID::Y, wire_c);
 				}
@@ -574,10 +574,10 @@ struct ExposePass : public Pass {
 					if (info.arst_polarity) {
 						module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
 					} else {
-						RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
-						c->parameters["\\A_SIGNED"] = 0;
-						c->parameters["\\A_WIDTH"] = 1;
-						c->parameters["\\Y_WIDTH"] = 1;
+						RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
+						c->parameters[ID::A_SIGNED] = 0;
+						c->parameters[ID::A_WIDTH] = 1;
+						c->parameters[ID::Y_WIDTH] = 1;
 						c->setPort(ID::A, info.sig_arst);
 						c->setPort(ID::Y, wire_r);
 					}
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index 18eeb37b5..5066485aa 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -43,7 +43,7 @@ struct FmcombineWorker
 
 	FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
 			opts(opts), design(design), original(design->module(orig_type)),
-			orig_type(orig_type), combined_type("$fmcombine" + orig_type.str())
+			orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type.c_str()))
 	{
 	}
 
@@ -106,7 +106,7 @@ struct FmcombineWorker
 
 		for (auto cell : original->cells()) {
 			if (design->module(cell->type) == nullptr) {
-				if (opts.anyeq && cell->type.in("$anyseq", "$anyconst")) {
+				if (opts.anyeq && cell->type.in(ID($anyseq), ID($anyconst))) {
 					Cell *gold = import_prim_cell(cell, "_gold");
 					for (auto &conn : cell->connections())
 						module->connect(import_sig(conn.second, "_gate"), gold->getPort(conn.first));
@@ -114,10 +114,10 @@ struct FmcombineWorker
 					Cell *gold = import_prim_cell(cell, "_gold");
 					Cell *gate = import_prim_cell(cell, "_gate");
 					if (opts.initeq) {
-						if (cell->type.in("$ff", "$dff", "$dffe",
-								"$dffsr", "$adff", "$dlatch", "$dlatchsr")) {
-							SigSpec gold_q = gold->getPort("\\Q");
-							SigSpec gate_q = gate->getPort("\\Q");
+						if (cell->type.in(ID($ff), ID($dff), ID($dffe),
+								ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr))) {
+							SigSpec gold_q = gold->getPort(ID::Q);
+							SigSpec gate_q = gate->getPort(ID::Q);
 							SigSpec en = module->Initstate(NEW_ID);
 							SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q);
 							module->addAssume(NEW_ID, eq, en);
diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc
index f3f00b382..555a28dc6 100644
--- a/passes/sat/fminit.cc
+++ b/passes/sat/fminit.cc
@@ -147,7 +147,7 @@ struct FminitPass : public Pass {
 					SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0;
 
 					Wire *outwire = module->addWire(NEW_ID);
-					outwire->attributes[ID(init)] = i > 0 ? State::S0 : State::S1;
+					outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1;
 
 					if (clksig.empty())
 						module->addFf(NEW_ID, insig, outwire);
@@ -161,7 +161,7 @@ struct FminitPass : public Pass {
 				if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty())
 				{
 					Wire *ffwire = module->addWire(NEW_ID);
-					ffwire->attributes[ID(init)] = State::S0;
+					ffwire->attributes[ID::init] = State::S0;
 					SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]);
 
 					if (clksig.empty())
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 020e2a74c..5dfd7bd3f 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -731,7 +731,7 @@ struct FreduceWorker
 					{
 						inv_sig = module->addWire(NEW_ID);
 
-						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
+						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_));
 						inv_cell->setPort(ID::A, grp[0].bit);
 						inv_cell->setPort(ID::Y, inv_sig);
 					}
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index f5bc251c2..aeece9b94 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -116,8 +116,8 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	miter_module->name = miter_name;
 	design->add(miter_module);
 
-	RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
-	RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);
+	RTLIL::Cell *gold_cell = miter_module->addCell(ID(gold), gold_name);
+	RTLIL::Cell *gate_cell = miter_module->addCell(ID(gate), gate_name);
 
 	RTLIL::SigSpec all_conditions;
 
@@ -149,12 +149,12 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 			{
 				RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width);
 				for (int i = 0; i < w_gold->width; i++) {
-					RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
-					eqx_cell->parameters["\\A_WIDTH"] = 1;
-					eqx_cell->parameters["\\B_WIDTH"] = 1;
-					eqx_cell->parameters["\\Y_WIDTH"] = 1;
-					eqx_cell->parameters["\\A_SIGNED"] = 0;
-					eqx_cell->parameters["\\B_SIGNED"] = 0;
+					RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx));
+					eqx_cell->parameters[ID::A_WIDTH] = 1;
+					eqx_cell->parameters[ID::B_WIDTH] = 1;
+					eqx_cell->parameters[ID::Y_WIDTH] = 1;
+					eqx_cell->parameters[ID::A_SIGNED] = 0;
+					eqx_cell->parameters[ID::B_SIGNED] = 0;
 					eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i));
 					eqx_cell->setPort(ID::B, RTLIL::State::Sx);
 					eqx_cell->setPort(ID::Y, gold_x.extract(i, 1));
@@ -163,32 +163,32 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
 				RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width);
 
-				RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
-				or_gold_cell->parameters["\\A_WIDTH"] = w_gold->width;
-				or_gold_cell->parameters["\\B_WIDTH"] = w_gold->width;
-				or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width;
-				or_gold_cell->parameters["\\A_SIGNED"] = 0;
-				or_gold_cell->parameters["\\B_SIGNED"] = 0;
+				RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or));
+				or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width;
+				or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width;
+				or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width;
+				or_gold_cell->parameters[ID::A_SIGNED] = 0;
+				or_gold_cell->parameters[ID::B_SIGNED] = 0;
 				or_gold_cell->setPort(ID::A, w_gold);
 				or_gold_cell->setPort(ID::B, gold_x);
 				or_gold_cell->setPort(ID::Y, gold_masked);
 
-				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
-				or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width;
-				or_gate_cell->parameters["\\B_WIDTH"] = w_gate->width;
-				or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width;
-				or_gate_cell->parameters["\\A_SIGNED"] = 0;
-				or_gate_cell->parameters["\\B_SIGNED"] = 0;
+				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or));
+				or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width;
+				or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width;
+				or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width;
+				or_gate_cell->parameters[ID::A_SIGNED] = 0;
+				or_gate_cell->parameters[ID::B_SIGNED] = 0;
 				or_gate_cell->setPort(ID::A, w_gate);
 				or_gate_cell->setPort(ID::B, gold_x);
 				or_gate_cell->setPort(ID::Y, gate_masked);
 
-				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
-				eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
-				eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
-				eq_cell->parameters["\\Y_WIDTH"] = 1;
-				eq_cell->parameters["\\A_SIGNED"] = 0;
-				eq_cell->parameters["\\B_SIGNED"] = 0;
+				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
+				eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
+				eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
+				eq_cell->parameters[ID::Y_WIDTH] = 1;
+				eq_cell->parameters[ID::A_SIGNED] = 0;
+				eq_cell->parameters[ID::B_SIGNED] = 0;
 				eq_cell->setPort(ID::A, gold_masked);
 				eq_cell->setPort(ID::B, gate_masked);
 				eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
@@ -196,12 +196,12 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 			}
 			else
 			{
-				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
-				eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
-				eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
-				eq_cell->parameters["\\Y_WIDTH"] = 1;
-				eq_cell->parameters["\\A_SIGNED"] = 0;
-				eq_cell->parameters["\\B_SIGNED"] = 0;
+				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
+				eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
+				eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
+				eq_cell->parameters[ID::Y_WIDTH] = 1;
+				eq_cell->parameters[ID::A_SIGNED] = 0;
+				eq_cell->parameters[ID::B_SIGNED] = 0;
 				eq_cell->setPort(ID::A, w_gold);
 				eq_cell->setPort(ID::B, w_gate);
 				eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
@@ -220,29 +220,29 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	}
 
 	if (all_conditions.size() != 1) {
-		RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and");
-		reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
-		reduce_cell->parameters["\\Y_WIDTH"] = 1;
-		reduce_cell->parameters["\\A_SIGNED"] = 0;
+		RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and));
+		reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+		reduce_cell->parameters[ID::Y_WIDTH] = 1;
+		reduce_cell->parameters[ID::A_SIGNED] = 0;
 		reduce_cell->setPort(ID::A, all_conditions);
 		reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
 		all_conditions = reduce_cell->getPort(ID::Y);
 	}
 
 	if (flag_make_assert) {
-		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
+		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert));
 		assert_cell->setPort(ID::A, all_conditions);
-		assert_cell->setPort("\\EN", State::S1);
+		assert_cell->setPort(ID::EN, State::S1);
 	}
 
-	RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger");
+	RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger));
 	w_trigger->port_output = true;
 
-	RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not");
-	not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
-	not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
-	not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
-	not_cell->parameters["\\A_SIGNED"] = 0;
+	RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not));
+	not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+	not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+	not_cell->parameters[ID::Y_WIDTH] = w_trigger->width;
+	not_cell->parameters[ID::A_SIGNED] = 0;
 	not_cell->setPort(ID::A, all_conditions);
 	not_cell->setPort(ID::Y, w_trigger);
 
@@ -298,7 +298,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
 		for (auto wire : module->wires())
 			wire->port_output = false;
 
-	Wire *trigger = module->addWire("\\trigger");
+	Wire *trigger = module->addWire(ID(trigger));
 	trigger->port_output = true;
 	module->fixup_ports();
 
@@ -312,13 +312,13 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
 	vector<Cell*> cell_list = module->cells();
 	for (auto cell : cell_list)
 	{
-		if (!cell->type.in("$assert", "$assume"))
+		if (!cell->type.in(ID($assert), ID($assume)))
 			continue;
 
 		SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1);
-		SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
+		SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1);
 
-		if (cell->type == "$assert") {
+		if (cell->type == ID($assert)) {
 			assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
 		} else {
 			assume_signals.append(module->And(NEW_ID, is_active, is_enabled));
@@ -334,7 +334,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
 	else
 	{
 		Wire *assume_q = module->addWire(NEW_ID);
-		assume_q->attributes["\\init"] = State::S0;
+		assume_q->attributes[ID::init] = State::S0;
 		assume_signals.append(assume_q);
 
 		SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 8ae572ad1..6acdbc800 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -258,11 +258,11 @@ struct SatHelper
 
 			for (auto &it : module->wires_)
 			{
-				if (it.second->attributes.count("\\init") == 0)
+				if (it.second->attributes.count(ID::init) == 0)
 					continue;
 
 				RTLIL::SigSpec lhs = sigmap(it.second);
-				RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
+				RTLIL::SigSpec rhs = it.second->attributes.at(ID::init);
 				log_assert(lhs.size() == rhs.size());
 
 				RTLIL::SigSpec removed_bits;
@@ -518,9 +518,9 @@ struct SatHelper
 				} else {
 					for (auto &d : drivers)
 					for (auto &p : d->connections()) {
-						if (d->type == "$dff" && p.first == "\\CLK")
+						if (d->type == ID($dff) && p.first == ID::CLK)
 							continue;
-						if (d->type.begins_with("$_DFF_") && p.first == "\\C")
+						if (d->type.begins_with("$_DFF_") && p.first == ID::C)
 							continue;
 						queued_signals.add(handled_signals.remove(sigmap(p.second)));
 					}
@@ -1354,8 +1354,8 @@ struct SatPass : public Pass {
 		if (show_regs) {
 			pool<Wire*> reg_wires;
 			for (auto cell : module->cells()) {
-				if (cell->type == "$dff" || cell->type.begins_with("$_DFF_"))
-					for (auto bit : cell->getPort("\\Q"))
+				if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_"))
+					for (auto bit : cell->getPort(ID::Q))
 						if (bit.wire)
 							reg_wires.insert(bit.wire);
 			}
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index c3e84ead5..59bf5a712 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -108,8 +108,8 @@ struct SimInstance
 				}
 			}
 
-			if (wire->attributes.count("\\init")) {
-				Const initval = wire->attributes.at("\\init");
+			if (wire->attributes.count(ID::init)) {
+				Const initval = wire->attributes.at(ID::init);
 				for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
 					if (initval[i] == State::S0 || initval[i] == State::S1) {
 						state_nets[sig[i]] = initval[i];
@@ -132,24 +132,24 @@ struct SimInstance
 						upd_cells[bit].insert(cell);
 			}
 
-			if (cell->type.in("$dff")) {
+			if (cell->type.in(ID($dff))) {
 				ff_state_t ff;
 				ff.past_clock = State::Sx;
-				ff.past_d = Const(State::Sx, cell->getParam("\\WIDTH").as_int());
+				ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int());
 				ff_database[cell] = ff;
 			}
 
-			if (cell->type == "$mem")
+			if (cell->type == ID($mem))
 			{
 				mem_state_t mem;
 
-				mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort("\\WR_CLK")));
-				mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort("\\WR_EN")));
-				mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort("\\WR_ADDR")));
-				mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort("\\WR_DATA")));
+				mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort(ID::WR_CLK)));
+				mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort(ID::WR_EN)));
+				mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort(ID::WR_ADDR)));
+				mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort(ID::WR_DATA)));
 
-				mem.data = cell->getParam("\\INIT");
-				int sz = cell->getParam("\\SIZE").as_int() * cell->getParam("\\WIDTH").as_int();
+				mem.data = cell->getParam(ID::INIT);
+				int sz = cell->getParam(ID::SIZE).as_int() * cell->getParam(ID::WIDTH).as_int();
 
 				if (GetSize(mem.data) > sz)
 					mem.data.bits.resize(sz);
@@ -160,7 +160,7 @@ struct SimInstance
 				mem_database[cell] = mem;
 			}
 
-			if (cell->type.in("$assert", "$cover", "$assume")) {
+			if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
 				formal_database.insert(cell);
 			}
 		}
@@ -173,7 +173,7 @@ struct SimInstance
 				ff_state_t &ff = it.second;
 				zinit(ff.past_d);
 
-				SigSpec qsig = cell->getPort("\\Q");
+				SigSpec qsig = cell->getPort(ID::Q);
 				Const qdata = get_state(qsig);
 				zinit(qdata);
 				set_state(qsig, qdata);
@@ -256,18 +256,18 @@ struct SimInstance
 		{
 			mem_state_t &mem = mem_database.at(cell);
 
-			int num_rd_ports = cell->getParam("\\RD_PORTS").as_int();
+			int num_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
 
-			int size = cell->getParam("\\SIZE").as_int();
-			int offset = cell->getParam("\\OFFSET").as_int();
-			int abits = cell->getParam("\\ABITS").as_int();
-			int width = cell->getParam("\\WIDTH").as_int();
+			int size = cell->getParam(ID::SIZE).as_int();
+			int offset = cell->getParam(ID::OFFSET).as_int();
+			int abits = cell->getParam(ID::ABITS).as_int();
+			int width = cell->getParam(ID::WIDTH).as_int();
 
-			if (cell->getParam("\\RD_CLK_ENABLE").as_bool())
+			if (cell->getParam(ID::RD_CLK_ENABLE).as_bool())
 				log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(cell));
 
-			SigSpec rd_addr_sig = cell->getPort("\\RD_ADDR");
-			SigSpec rd_data_sig = cell->getPort("\\RD_DATA");
+			SigSpec rd_addr_sig = cell->getPort(ID::RD_ADDR);
+			SigSpec rd_data_sig = cell->getPort(ID::RD_DATA);
 
 			for (int port_idx = 0; port_idx < num_rd_ports; port_idx++)
 			{
@@ -305,15 +305,15 @@ struct SimInstance
 
 			has_a = cell->hasPort(ID::A);
 			has_b = cell->hasPort(ID::B);
-			has_c = cell->hasPort("\\C");
-			has_d = cell->hasPort("\\D");
+			has_c = cell->hasPort(ID::C);
+			has_d = cell->hasPort(ID::D);
 			has_s = cell->hasPort(ID::S);
 			has_y = cell->hasPort(ID::Y);
 
 			if (has_a) sig_a = cell->getPort(ID::A);
 			if (has_b) sig_b = cell->getPort(ID::B);
-			if (has_c) sig_c = cell->getPort("\\C");
-			if (has_d) sig_d = cell->getPort("\\D");
+			if (has_c) sig_c = cell->getPort(ID::C);
+			if (has_d) sig_d = cell->getPort(ID::D);
 			if (has_s) sig_s = cell->getPort(ID::S);
 			if (has_y) sig_y = cell->getPort(ID::Y);
 
@@ -403,16 +403,16 @@ struct SimInstance
 			Cell *cell = it.first;
 			ff_state_t &ff = it.second;
 
-			if (cell->type.in("$dff"))
+			if (cell->type.in(ID($dff)))
 			{
-				bool clkpol = cell->getParam("\\CLK_POLARITY").as_bool();
-				State current_clock = get_state(cell->getPort("\\CLK"))[0];
+				bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool();
+				State current_clock = get_state(cell->getPort(ID::CLK))[0];
 
 				if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
 						(ff.past_clock == State::S0 || current_clock != State::S0))
 					continue;
 
-				if (set_state(cell->getPort("\\Q"), ff.past_d))
+				if (set_state(cell->getPort(ID::Q), ff.past_d))
 					did_something = true;
 			}
 		}
@@ -422,16 +422,16 @@ struct SimInstance
 			Cell *cell = it.first;
 			mem_state_t &mem = it.second;
 
-			int num_wr_ports = cell->getParam("\\WR_PORTS").as_int();
+			int num_wr_ports = cell->getParam(ID::WR_PORTS).as_int();
 
-			int size = cell->getParam("\\SIZE").as_int();
-			int offset = cell->getParam("\\OFFSET").as_int();
-			int abits = cell->getParam("\\ABITS").as_int();
-			int width = cell->getParam("\\WIDTH").as_int();
+			int size = cell->getParam(ID::SIZE).as_int();
+			int offset = cell->getParam(ID::OFFSET).as_int();
+			int abits = cell->getParam(ID::ABITS).as_int();
+			int width = cell->getParam(ID::WIDTH).as_int();
 
-			Const wr_clk_enable = cell->getParam("\\WR_CLK_ENABLE");
-			Const wr_clk_polarity = cell->getParam("\\WR_CLK_POLARITY");
-			Const current_wr_clk  = get_state(cell->getPort("\\WR_CLK"));
+			Const wr_clk_enable = cell->getParam(ID::WR_CLK_ENABLE);
+			Const wr_clk_polarity = cell->getParam(ID::WR_CLK_POLARITY);
+			Const current_wr_clk  = get_state(cell->getPort(ID::WR_CLK));
 
 			for (int port_idx = 0; port_idx < num_wr_ports; port_idx++)
 			{
@@ -439,9 +439,9 @@ struct SimInstance
 
 				if (wr_clk_enable[port_idx] == State::S0)
 				{
-					addr = get_state(cell->getPort("\\WR_ADDR").extract(port_idx*abits, abits));
-					data = get_state(cell->getPort("\\WR_DATA").extract(port_idx*width, width));
-					enable = get_state(cell->getPort("\\WR_EN").extract(port_idx*width, width));
+					addr = get_state(cell->getPort(ID::WR_ADDR).extract(port_idx*abits, abits));
+					data = get_state(cell->getPort(ID::WR_DATA).extract(port_idx*width, width));
+					enable = get_state(cell->getPort(ID::WR_EN).extract(port_idx*width, width));
 				}
 				else
 				{
@@ -485,9 +485,9 @@ struct SimInstance
 			Cell *cell = it.first;
 			ff_state_t &ff = it.second;
 
-			if (cell->type.in("$dff")) {
-				ff.past_clock = get_state(cell->getPort("\\CLK"))[0];
-				ff.past_d = get_state(cell->getPort("\\D"));
+			if (cell->type.in(ID($dff))) {
+				ff.past_clock = get_state(cell->getPort(ID::CLK))[0];
+				ff.past_d = get_state(cell->getPort(ID::D));
 			}
 		}
 
@@ -496,10 +496,10 @@ struct SimInstance
 			Cell *cell = it.first;
 			mem_state_t &mem = it.second;
 
-			mem.past_wr_clk  = get_state(cell->getPort("\\WR_CLK"));
-			mem.past_wr_en   = get_state(cell->getPort("\\WR_EN"));
-			mem.past_wr_addr = get_state(cell->getPort("\\WR_ADDR"));
-			mem.past_wr_data = get_state(cell->getPort("\\WR_DATA"));
+			mem.past_wr_clk  = get_state(cell->getPort(ID::WR_CLK));
+			mem.past_wr_en   = get_state(cell->getPort(ID::WR_EN));
+			mem.past_wr_addr = get_state(cell->getPort(ID::WR_ADDR));
+			mem.past_wr_data = get_state(cell->getPort(ID::WR_DATA));
 		}
 
 		for (auto cell : formal_database)
@@ -509,15 +509,15 @@ struct SimInstance
 				label = cell->attributes.at(ID::src).decode_string();
 
 			State a = get_state(cell->getPort(ID::A))[0];
-			State en = get_state(cell->getPort("\\EN"))[0];
+			State en = get_state(cell->getPort(ID::EN))[0];
 
-			if (cell->type == "$cover" && en == State::S1 && a != State::S1)
+			if (cell->type == ID($cover) && en == State::S1 && a != State::S1)
 				log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str());
 
-			if (cell->type == "$assume" && en == State::S1 && a != State::S1)
+			if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
 				log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
 
-			if (cell->type == "$assert" && en == State::S1 && a != State::S1)
+			if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
 				log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
 		}
 
@@ -533,22 +533,22 @@ struct SimInstance
 		wbmods.insert(module);
 
 		for (auto wire : module->wires())
-			wire->attributes.erase("\\init");
+			wire->attributes.erase(ID::init);
 
 		for (auto &it : ff_database)
 		{
 			Cell *cell = it.first;
-			SigSpec sig_q = cell->getPort("\\Q");
+			SigSpec sig_q = cell->getPort(ID::Q);
 			Const initval = get_state(sig_q);
 
 			for (int i = 0; i < GetSize(sig_q); i++)
 			{
 				Wire *w = sig_q[i].wire;
 
-				if (w->attributes.count("\\init") == 0)
-					w->attributes["\\init"] = Const(State::Sx, GetSize(w));
+				if (w->attributes.count(ID::init) == 0)
+					w->attributes[ID::init] = Const(State::Sx, GetSize(w));
 
-				w->attributes["\\init"][sig_q[i].offset] = initval[i];
+				w->attributes[ID::init][sig_q[i].offset] = initval[i];
 			}
 		}
 
@@ -564,7 +564,7 @@ struct SimInstance
 				initval.bits.pop_back();
 			}
 
-			cell->setParam("\\INIT", initval);
+			cell->setParam(ID::INIT, initval);
 		}
 
 		for (auto it : children)