aboutsummaryrefslogtreecommitdiffstats
path: root/passes/sat
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2019-02-27 11:45:13 -0800
committerClifford Wolf <clifford@clifford.at>2019-02-27 11:45:13 -0800
commit63be3f3bab9293cf5b8f7416fce13cdeaa030727 (patch)
tree23d56307202d8da4bc9059c55b61915f27e0dee2 /passes/sat
parenta58dbcf2bae38835cdc2964718d4562ae4be4cc5 (diff)
downloadyosys-63be3f3bab9293cf5b8f7416fce13cdeaa030727.tar.gz
yosys-63be3f3bab9293cf5b8f7416fce13cdeaa030727.tar.bz2
yosys-63be3f3bab9293cf5b8f7416fce13cdeaa030727.zip
Improvements in "supercover" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/sat')
-rw-r--r--passes/sat/supercover.cc20
1 files changed, 18 insertions, 2 deletions
diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc
index 9b208b0bf..ba44f02d8 100644
--- a/passes/sat/supercover.cc
+++ b/passes/sat/supercover.cc
@@ -54,17 +54,33 @@ struct SupercoverPass : public Pass {
for (auto module : design->selected_modules())
{
+ SigMap sigmap(module);
+ pool<SigBit> handled_bits;
+
int cnt_wire = 0, cnt_bits = 0;
log("Adding cover cells to module %s.\n", log_id(module));
for (auto wire : module->selected_wires())
{
+ bool counted_wire = false;
std::string src = wire->get_src_attribute();
- cnt_wire++;
- for (auto bit : SigSpec(wire))
+
+ for (auto bit : sigmap(SigSpec(wire)))
{
+ if (bit.wire == nullptr)
+ continue;
+
+ if (handled_bits.count(bit))
+ continue;
+
SigSpec inv = module->Not(NEW_ID, bit);
module->addCover(NEW_ID, bit, State::S1, src);
module->addCover(NEW_ID, inv, State::S1, src);
+
+ handled_bits.insert(bit);
+ if (!counted_wire) {
+ counted_wire = false;
+ cnt_wire++;
+ }
cnt_bits++;
}
}