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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-27 09:24:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-27 09:24:59 -0700 |
| commit | 28133432bea4a3fa01cd2f5e82a52a853cfccb84 (patch) | |
| tree | 911463ee1d02f3f3649e8137d11152cf7009c9ab /passes/sat | |
| parent | 00387f39277ab817b3b17e72b59793e6d5dfcde8 (diff) | |
| download | yosys-28133432bea4a3fa01cd2f5e82a52a853cfccb84.tar.gz yosys-28133432bea4a3fa01cd2f5e82a52a853cfccb84.tar.bz2 yosys-28133432bea4a3fa01cd2f5e82a52a853cfccb84.zip | |
Ignore all 1'bx in (* init *)
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sat.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index bcc690fa3..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,9 +268,7 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (bit.is_fully_const() && rhs[i] == State::Sx) - rhs[i] = bit; - if (!satgen.initial_state.check_all(bit)) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); |