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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-17 14:56:58 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-17 14:56:58 +0200 |
| commit | 15fb56697a7ecf5378ffbb0e6ea8716ceddb1809 (patch) | |
| tree | 80ca52f75b77c25c923e50476ca2fed061dd81af /passes/sat | |
| parent | 6425d34e73914f98bcd355a41700651edab1eb93 (diff) | |
| download | yosys-15fb56697a7ecf5378ffbb0e6ea8716ceddb1809.tar.gz yosys-15fb56697a7ecf5378ffbb0e6ea8716ceddb1809.tar.bz2 yosys-15fb56697a7ecf5378ffbb0e6ea8716ceddb1809.zip | |
Bugfix in "miter -assert" handling of assumptions
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/miter.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 341a6bac8..9e150b60c 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -338,12 +338,12 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL else { Wire *assume_q = module->addWire(NEW_ID); - assume_q->attributes["\\init"] = State::S1; + assume_q->attributes["\\init"] = State::S0; assume_signals.append(assume_q); SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals); SigSpec assume_ok = module->Not(NEW_ID, assume_nok); - module->addFf(NEW_ID, assume_ok, assume_q); + module->addFf(NEW_ID, assume_nok, assume_q); SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals); module->addAnd(NEW_ID, assert_fail, assume_ok, trigger); |