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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-01 22:19:24 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-04 22:13:27 +0000 |
| commit | 0ca3a8e94f9bff1e262e6bea1796cc125fa24b92 (patch) | |
| tree | 4db97028e9739d4b5bd92cf6c792204c57eca188 /passes/sat | |
| parent | 1db73e8dd24842b62c694db96035e9d7687d03ae (diff) | |
| download | yosys-0ca3a8e94f9bff1e262e6bea1796cc125fa24b92.tar.gz yosys-0ca3a8e94f9bff1e262e6bea1796cc125fa24b92.tar.bz2 yosys-0ca3a8e94f9bff1e262e6bea1796cc125fa24b92.zip | |
Improve style in `passes/sat/qbfsat.cc`.
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/qbfsat.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index bfc1ae161..8b7ccc685 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -227,14 +227,13 @@ void assume_miter_outputs(RTLIL::Module *module) { if (wires_to_assume.size() == 0) return; else { - log("Adding $assume cell for outputs: "); + log("Adding $assume cell for output(s): "); for (auto w : wires_to_assume) log("\"%s\" ", w->name.c_str()); log("\n"); } - unsigned long i = 0; - while (wires_to_assume.size() > 1) { + for(auto i = 0; wires_to_assume.size() > 1; ++i) { std::vector<RTLIL::Wire *> buf; for (auto j = 0; j + 1 < GetSize(wires_to_assume); j += 2) { std::stringstream strstr; strstr << i << "_" << j; @@ -245,7 +244,6 @@ void assume_miter_outputs(RTLIL::Module *module) { if (wires_to_assume.size() % 2 == 1) buf.push_back(wires_to_assume[wires_to_assume.size() - 1]); wires_to_assume.swap(buf); - ++i; } #ifndef NDEBUG |