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| author | Clifford Wolf <clifford@clifford.at> | 2017-05-28 11:59:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-05-28 11:59:05 +0200 |
| commit | 05df3dbee434dc206c02314d4ff7d2a6faee1c4b (patch) | |
| tree | f8dfc193a57cdd1d9a5647805b5685a465dcf0ac /passes/sat | |
| parent | 9ed4c9d710e8ffc9bc33ecfe8f5650fc45cf5bc2 (diff) | |
| download | yosys-05df3dbee434dc206c02314d4ff7d2a6faee1c4b.tar.gz yosys-05df3dbee434dc206c02314d4ff7d2a6faee1c4b.tar.bz2 yosys-05df3dbee434dc206c02314d4ff7d2a6faee1c4b.zip | |
Add "setundef -anyseq"
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/freduce.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 77263f6a2..a3028bfce 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -687,7 +687,8 @@ struct FreduceWorker } std::map<RTLIL::SigBit, int> bitusage; - module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage)); + CountBitUsage bitusage_worker(sigmap, bitusage); + module->rewrite_sigspecs(bitusage_worker); if (!dump_prefix.empty()) dump(); |