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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:22:47 -0700 |
| commit | 046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497 (patch) | |
| tree | 900ad3764a73cb81396bcf0c0be1bc92c4df135d /passes/sat | |
| parent | 3486235338faa1377bb4e1a8981a45b4ee6edfa9 (diff) | |
| download | yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.gz yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.tar.bz2 yosys-046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497.zip | |
Use State::S{0,1}
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/eval.cc | 4 | ||||
| -rw-r--r-- | passes/sat/miter.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 008cd2dfa..e0bb439f4 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -47,8 +47,8 @@ struct BruteForceEquivChecker { if (inputs.size() < mod1_inputs.size()) { RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs; - inputs0.append(RTLIL::Const(0, 1)); - inputs1.append(RTLIL::Const(1, 1)); + inputs0.append(State::S0); + inputs1.append(State::S1); run_checker(inputs0); run_checker(inputs1); return; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 1a886af70..e1da1a9e6 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -236,7 +236,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); assert_cell->setPort("\\A", all_conditions); - assert_cell->setPort("\\EN", RTLIL::SigSpec(1, 1)); + assert_cell->setPort("\\EN", State::S1); } RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger"); |