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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 18:43:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 18:43:17 -0700 |
| commit | 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb (patch) | |
| tree | 15030ecf9f8f0be8a553f744ed2a4322e999dc1a /passes/pmgen | |
| parent | ed7be3e6b68521b2f147034f811a19bd7af86d1a (diff) | |
| download | yosys-7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.tar.gz yosys-7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.tar.bz2 yosys-7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.zip | |
Trim shiftx_width when upper bits are 1'bx
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 3f4efebe9..d3ba0109f 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -164,6 +164,11 @@ endmatch code shiftx_width shiftx_width = param(shiftx, \A_WIDTH).as_int(); + while (shiftx_width > 1) { + if (port(shiftx, \A)[shiftx_width-1] != State::Sx) + break; + --shiftx_width; + } endcode match first @@ -177,7 +182,7 @@ code chain.push_back(first); subpattern(tail); finally - if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int()) + if (GetSize(chain) == shiftx_width) accept; chain.clear(); endcode |