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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 17:36:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 17:36:38 -0700 |
| commit | ed7be3e6b68521b2f147034f811a19bd7af86d1a (patch) | |
| tree | 0bc6626651c7f123b5df7f68ebc51db03db5a47e /passes/pmgen | |
| parent | 15188033da68c89c409af0839f22e6acc573abb7 (diff) | |
| download | yosys-ed7be3e6b68521b2f147034f811a19bd7af86d1a.tar.gz yosys-ed7be3e6b68521b2f147034f811a19bd7af86d1a.tar.bz2 yosys-ed7be3e6b68521b2f147034f811a19bd7af86d1a.zip | |
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Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index ce77a3308..71112e3bc 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -218,6 +218,10 @@ struct XilinxSrlPass : public Pass { do { auto pm = xilinx_srl_pm(module, module->selected_cells()); pm.ud_variable.minlen = minlen; + // Since `nusers` does not count module ports as a user, + // and since `sigmap` does not always make such ports + // the canonical signal.. need to maintain a pool these + // ourselves for (auto p : module->ports) { auto w = module->wire(p); if (w->port_output) |