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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:40:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:40:17 -0700 |
| commit | 37b0fc17e32d84698b6fa4ccbcff40155351e290 (patch) | |
| tree | 37f85486d79d803e9996ec20d903ba1faf3a4a44 /passes/pmgen | |
| parent | 95db2489bdb515a2e9d3a995574adc8c1071d3c0 (diff) | |
| download | yosys-37b0fc17e32d84698b6fa4ccbcff40155351e290.tar.gz yosys-37b0fc17e32d84698b6fa4ccbcff40155351e290.tar.bz2 yosys-37b0fc17e32d84698b6fa4ccbcff40155351e290.zip | |
Re-enable sign extension for C input
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 5af48e4d2..ce75be0e9 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -322,10 +322,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) opmode[5] = State::S1; if (opmode[4] != State::S0) { - //if (st.postAddMuxAB == "\\A") - // st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool()); - //else - // st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool()); + if (st.postAddMuxAB == "\\A") + st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool()); + else + st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool()); cell->setPort("\\C", st.sigC); } |