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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 12:43:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 22:31:04 -0700 |
| commit | 7de9c33931020068b285e262bbf239385fcb5c2d (patch) | |
| tree | 7b46e853474ce4c3b1cccc0eb321cb1a611aa400 /passes/pmgen/xilinx_dsp_CREG.pmg | |
| parent | 983068103e24c33a1b70eb90dd72fdfaf292e1bd (diff) | |
| download | yosys-7de9c33931020068b285e262bbf239385fcb5c2d.tar.gz yosys-7de9c33931020068b285e262bbf239385fcb5c2d.tar.bz2 yosys-7de9c33931020068b285e262bbf239385fcb5c2d.zip | |
Fix TODOs
Diffstat (limited to 'passes/pmgen/xilinx_dsp_CREG.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_CREG.pmg | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index 38a5a8d24..5697ee737 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -79,11 +79,6 @@ endcode // (attached to at most two $mux cells that implement clock-enable or // reset functionality, using a subpattern discussed below) code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock - // TODO: Any downside to allowing this? - // If this DSP implements an accumulator, do not attempt to match - if (sigC == sigP) - reject; - argQ = sigC; subpattern(in_dffe); if (dff) { |