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authorEddie Hung <eddie@fpgeh.com>2019-10-04 12:43:19 -0700
committerEddie Hung <eddie@fpgeh.com>2019-10-04 22:31:04 -0700
commit983068103e24c33a1b70eb90dd72fdfaf292e1bd (patch)
tree50daa1a6a823026e662c85246419dc56eb2bbe84 /passes/pmgen/xilinx_dsp_CREG.pmg
parentcf82b38478e598c915d14d595b554fc122034850 (diff)
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Consistency
Diffstat (limited to 'passes/pmgen/xilinx_dsp_CREG.pmg')
-rw-r--r--passes/pmgen/xilinx_dsp_CREG.pmg6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index a20d3cdce..38a5a8d24 100644
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -45,7 +45,7 @@ match dsp
select nusers(port(dsp, \C, SigSpec())) > 1
endmatch
-code sigC sigP
+code sigC sigP clock
unextend = [](const SigSpec &sig) {
int i;
for (i = GetSize(sig)-1; i > 0; i--)
@@ -71,6 +71,8 @@ code sigC sigP
}
else
sigP = P;
+
+ clock = port(dsp, \CLK, SigBit());
endcode
// (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
@@ -82,8 +84,6 @@ code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
if (sigC == sigP)
reject;
- clock = port(dsp, \CLK, SigBit());
-
argQ = sigC;
subpattern(in_dffe);
if (dff) {