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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 21:28:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 21:28:28 -0700 |
| commit | 53ca536d674ade382da16adddfb02db7e970acef (patch) | |
| tree | 50b41c521eb410945ce17b32f83862f5418aa2ba /passes/pmgen/xilinx_dsp.pmg | |
| parent | 5a2fc6fcb5141573cbfcebdec4354fc11056a8f4 (diff) | |
| download | yosys-53ca536d674ade382da16adddfb02db7e970acef.tar.gz yosys-53ca536d674ade382da16adddfb02db7e970acef.tar.bz2 yosys-53ca536d674ade382da16adddfb02db7e970acef.zip | |
ffAmuxAB -> ffAenpol
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index fa490146c..579935869 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -2,7 +2,8 @@ pattern xilinx_dsp state <SigBit> clock state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP -state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB +state <IdString> ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB +state <bool> ffAenpol match dsp select dsp->type.in(\DSP48E1) @@ -69,9 +70,10 @@ match ffAmux filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA) slice offset GetSize(port(ffAmux, \Y)) filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA - choice <IdString> AB {\A, \B} - filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, AB).extract(offset, GetSize(sigffAmux)) == sigffAmux - set ffAmuxAB AB + choice <IdString> BA {\B, \A} + filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, BA).extract(offset, GetSize(sigffAmux)) == sigffAmux + define <bool> pol (BA == \B) + set ffAenpol pol semioptional endmatch |