From 53ca536d674ade382da16adddfb02db7e970acef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 21:28:28 -0700
Subject: ffAmuxAB -> ffAenpol

---
 passes/pmgen/xilinx_dsp.pmg | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'passes/pmgen/xilinx_dsp.pmg')

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index fa490146c..579935869 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,7 +2,8 @@ pattern xilinx_dsp
 
 state <SigBit> clock
 state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
-state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
+state <IdString> ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
+state <bool> ffAenpol
 
 match dsp
 	select dsp->type.in(\DSP48E1)
@@ -69,9 +70,10 @@ match ffAmux
 	filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
 	slice offset GetSize(port(ffAmux, \Y))
 	filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA
-	choice <IdString> AB {\A, \B}
-	filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, AB).extract(offset, GetSize(sigffAmux)) == sigffAmux
-	set ffAmuxAB AB
+	choice <IdString> BA {\B, \A}
+	filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, BA).extract(offset, GetSize(sigffAmux)) == sigffAmux
+	define <bool> pol (BA == \B)
+	set ffAenpol pol
 	semioptional
 endmatch
 
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