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authorEddie Hung <eddie@fpgeh.com>2020-04-22 17:43:25 -0700
committerEddie Hung <eddie@fpgeh.com>2020-04-22 17:43:25 -0700
commit592baebd22ab1c80512b6f91926d90b33393285e (patch)
treef4da9868f765321832f52e8139ec745a5e98a520 /passes/pmgen/peepopt_shiftmul.pmg
parentdb09e96dff63b7b0fdb7010ad1965aaf261cbe2f (diff)
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xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
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