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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 17:43:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 17:43:25 -0700 |
| commit | 592baebd22ab1c80512b6f91926d90b33393285e (patch) | |
| tree | f4da9868f765321832f52e8139ec745a5e98a520 /passes | |
| parent | db09e96dff63b7b0fdb7010ad1965aaf261cbe2f (diff) | |
| download | yosys-592baebd22ab1c80512b6f91926d90b33393285e.tar.gz yosys-592baebd22ab1c80512b6f91926d90b33393285e.tar.bz2 yosys-592baebd22ab1c80512b6f91926d90b33393285e.zip | |
xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_cascade.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index a36edd9e5..8babb88e6 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -188,7 +188,7 @@ arg next // driven by the 'P' output of the previous DSP cell, and (c) has its // 'PCIN' port unused match nextP - select !param(nextP, \CREG).as_bool() + select !nextP->type.in(\DSP48E1) || !param(nextP, \CREG).as_bool() select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("11")) || (nextP->type.in(\DSP48E1) && port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")) select nusers(port(nextP, \C, SigSpec())) > 1 select nusers(port(nextP, \PCIN, SigSpec())) == 0 |