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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-13 13:39:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-09-13 13:39:39 +0200 |
| commit | a67d63714be52e4a4f789c2a82b6283748db8902 (patch) | |
| tree | ecb7c6ddb452362a988b7299ee696005940df045 /passes/opt | |
| parent | 4da6e19fe1c326bb86e68f4446597c2163f3fbb2 (diff) | |
| download | yosys-a67d63714be52e4a4f789c2a82b6283748db8902.tar.gz yosys-a67d63714be52e4a4f789c2a82b6283748db8902.tar.bz2 yosys-a67d63714be52e4a4f789c2a82b6283748db8902.zip | |
Fix handling of z_digit "?" and fix optimization of cmp with "z"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 00d7d6063..6cf66fb95 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (b.is_fully_const()) { + if (b.is_fully_undef()) { + RTLIL::SigSpec input = b; + ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y)))); + } else if (b.as_bool() == (cell->type == ID($eq))) { RTLIL::SigSpec input = b; ACTION_DO(ID::Y, cell->getPort(ID::A)); |