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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-13 13:39:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-09-13 13:39:39 +0200 |
| commit | a67d63714be52e4a4f789c2a82b6283748db8902 (patch) | |
| tree | ecb7c6ddb452362a988b7299ee696005940df045 | |
| parent | 4da6e19fe1c326bb86e68f4446597c2163f3fbb2 (diff) | |
| download | yosys-a67d63714be52e4a4f789c2a82b6283748db8902.tar.gz yosys-a67d63714be52e4a4f789c2a82b6283748db8902.tar.bz2 yosys-a67d63714be52e4a4f789c2a82b6283748db8902.zip | |
Fix handling of z_digit "?" and fix optimization of cmp with "z"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verilog/const2ast.cc | 6 | ||||
| -rw-r--r-- | passes/opt/opt_expr.cc | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 5da88a93f..49281f7e7 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -85,10 +85,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le digits.push_back(10 + *str - 'A'); else if (*str == 'x' || *str == 'X') digits.push_back(0xf0); - else if (*str == 'z' || *str == 'Z') + else if (*str == 'z' || *str == 'Z' || *str == '?') digits.push_back(0xf1); - else if (*str == '?') - digits.push_back(0xf2); str++; } @@ -112,8 +110,6 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx); else if (*it == 0xf1) data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz); - else if (*it == 0xf2) - data.push_back(RTLIL::Sa); else data.push_back((*it & bitmask) ? State::S1 : State::S0); } diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 00d7d6063..6cf66fb95 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (b.is_fully_const()) { + if (b.is_fully_undef()) { + RTLIL::SigSpec input = b; + ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y)))); + } else if (b.as_bool() == (cell->type == ID($eq))) { RTLIL::SigSpec input = b; ACTION_DO(ID::Y, cell->getPort(ID::A)); |