Removed RTLIL::SigSpec::expand() method

9 files changed, 135 insertions, 211 deletions

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 8cdd39b7a..ba27a3fc6 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -55,26 +55,23 @@ struct gate_t
 	char type;
 	int in1, in2, in3;
 	bool is_port;
-	RTLIL::SigSpec sig;
+	RTLIL::SigBit bit;
 };
 
 static int map_autoidx;
 static SigMap assign_map;
 static RTLIL::Module *module;
 static std::vector<gate_t> signal_list;
-static std::map<RTLIL::SigSpec, int> signal_map;
+static std::map<RTLIL::SigBit, int> signal_map;
 
 static bool clk_polarity;
 static RTLIL::SigSpec clk_sig;
 
-static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1)
+static int map_signal(RTLIL::SigBit bit, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1)
 {
-	assert(sig.size() == 1);
-	assert(sig.chunks().size() == 1);
+	assign_map.apply(bit);
 
-	assign_map.apply(sig);
-
-	if (signal_map.count(sig) == 0) {
+	if (signal_map.count(bit) == 0) {
 		gate_t gate;
 		gate.id = signal_list.size();
 		gate.type = -1;
@@ -82,12 +79,12 @@ static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int
 		gate.in2 = -1;
 		gate.in3 = -1;
 		gate.is_port = false;
-		gate.sig = sig;
+		gate.bit = bit;
 		signal_list.push_back(gate);
-		signal_map[sig] = gate.id;
+		signal_map[bit] = gate.id;
 	}
 
-	gate_t &gate = signal_list[signal_map[sig]];
+	gate_t &gate = signal_list[signal_map[bit]];
 
 	if (gate_type >= 0)
 		gate.type = gate_type;
@@ -103,12 +100,9 @@ static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int
 
 static void mark_port(RTLIL::SigSpec sig)
 {
-	assign_map.apply(sig);
-	sig.expand();
-	for (auto &c : sig.chunks()) {
-		if (c.wire != NULL && signal_map.count(c) > 0)
-			signal_list[signal_map[c]].is_port = true;
-	}
+	for (auto &bit : assign_map(sig))
+		if (bit.wire != NULL && signal_map.count(bit) > 0)
+			signal_list[signal_map[bit]].is_port = true;
 }
 
 static void extract_cell(RTLIL::Cell *cell, bool keepff)
@@ -229,7 +223,7 @@ static void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edge
 	}
 
 	for (auto n : nodes)
-		fprintf(f, "  n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].sig),
+		fprintf(f, "  n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
 				n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
 
 	for (auto &e : edges)
@@ -280,7 +274,7 @@ static void handle_loops()
 		int id = *workpool.begin();
 		workpool.erase(id);
 
-		// log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].sig));
+		// log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit));
 
 		for (int id2 : edges[id]) {
 			assert(in_edges_count[id2] > 0);
@@ -300,8 +294,8 @@ static void handle_loops()
 
 			for (auto &edge_it : edges) {
 				int id2 = edge_it.first;
-				RTLIL::Wire *w1 = signal_list[id1].sig.chunks()[0].wire;
-				RTLIL::Wire *w2 = signal_list[id2].sig.chunks()[0].wire;
+				RTLIL::Wire *w1 = signal_list[id1].bit.wire;
+				RTLIL::Wire *w2 = signal_list[id2].bit.wire;
 				if (w1 != NULL)
 					continue;
 				else if (w2 == NULL)
@@ -333,10 +327,10 @@ static void handle_loops()
 			for (int id2 : edges[id1]) {
 				if (first_line)
 					log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
-							log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig));
+							log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
 				else
 					log("                               %*s  %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
-							log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig));
+							log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
 				first_line = false;
 			}
 
@@ -357,7 +351,7 @@ static void handle_loops()
 			}
 			edges[id1].swap(edges[id3]);
 
-			module->connections.push_back(RTLIL::SigSig(signal_list[id3].sig, signal_list[id1].sig));
+			module->connections.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
 			dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
 		}
 	}
@@ -549,13 +543,12 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 	fprintf(f, "\n");
 
 	for (auto &si : signal_list)
-		fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig));
+		fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit));
 
 	for (auto &si : signal_list) {
-		assert(si.sig.size() == 1 && si.sig.chunks().size() == 1);
-		if (si.sig.chunks()[0].wire == NULL) {
+		if (si.bit.wire == NULL) {
 			fprintf(f, ".names n%d\n", si.id);
-			if (si.sig.chunks()[0].data.bits[0] == RTLIL::State::S1)
+			if (si.bit == RTLIL::State::S1)
 				fprintf(f, "1\n");
 		}
 	}
@@ -837,12 +830,12 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 				snprintf(buffer, 100, "\\n%d", si.id);
 				RTLIL::SigSig conn;
 				if (si.type >= 0) {
-					conn.first = si.sig;
+					conn.first = si.bit;
 					conn.second = RTLIL::SigSpec(module->wires[remap_name(buffer)]);
 					out_wires++;
 				} else {
 					conn.first = RTLIL::SigSpec(module->wires[remap_name(buffer)]);
-					conn.second = si.sig;
+					conn.second = si.bit;
 					in_wires++;
 				}
 				module->connections.push_back(conn);
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 23fc48d5d..0be36606d 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -233,14 +233,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 			if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {
 				del_wires.push_back(wire);
 			} else {
-				s1.expand();
-				s2.expand();
-				assert(s1.chunks().size() == s2.chunks().size());
+				assert(SIZE(s1) == SIZE(s2));
 				RTLIL::SigSig new_conn;
-				for (size_t i = 0; i < s1.chunks().size(); i++)
-					if (s1.chunks()[i] != s2.chunks()[i]) {
-						new_conn.first.append(s1.chunks()[i]);
-						new_conn.second.append(s2.chunks()[i]);
+				for (int i = 0; i < SIZE(s1); i++)
+					if (s1[i] != s2[i]) {
+						new_conn.first.append_bit(s1[i]);
+						new_conn.second.append_bit(s2[i]);
 					}
 				if (new_conn.first.size() > 0) {
 					new_conn.first.optimize();
@@ -257,9 +255,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire));
 		if (!used_signals_nodrivers.check_any(sig)) {
 			std::string unused_bits;
-			sig.expand();
-			for (size_t i = 0; i < sig.chunks().size(); i++) {
-				if (sig.chunks()[i].wire == NULL)
+			for (int i = 0; i < SIZE(sig); i++) {
+				if (sig[i].wire == NULL)
 					continue;
 				if (!used_signals_nodrivers.check_any(sig)) {
 					if (!unused_bits.empty())
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 9b89291b1..ff139854f 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -458,21 +458,19 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 
 			RTLIL::SigSpec new_a, new_b;
-			a.expand(), b.expand();
 
-			assert(a.chunks().size() == b.chunks().size());
-			for (size_t i = 0; i < a.chunks().size(); i++) {
-				if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] &&
-						a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) {
+			assert(SIZE(a) == SIZE(b));
+			for (int i = 0; i < SIZE(a); i++) {
+				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
 					RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
 					new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
 					replace_cell(module, cell, "empty", "\\Y", new_y);
 					goto next_cell;
 				}
-				if (a.chunks()[i] == b.chunks()[i])
+				if (a[i] == b[i])
 					continue;
-				new_a.append(a.chunks()[i]);
-				new_b.append(b.chunks()[i]);
+				new_a.append(a[i]);
+				new_b.append(b[i]);
 			}
 
 			if (new_a.size() == 0) {
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 61147f67a..dfcd55126 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -36,7 +36,11 @@ struct OptMuxtreeWorker
 	SigMap assign_map;
 	int removed_count;
 
-	typedef std::pair<RTLIL::Wire*,int> bitDef_t;
+        struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
+		bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
+		bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
+	};
+
 
 	struct bitinfo_t {
 		int num;
@@ -259,10 +263,8 @@ struct OptMuxtreeWorker
 	{
 		std::vector<int> results;
 		assign_map.apply(sig);
-		sig.expand();
-		for (auto &c : sig.chunks())
-			if (c.wire != NULL) {
-				bitDef_t bit(c.wire, c.offset);
+		for (auto &bit : sig)
+			if (bit.wire != NULL) {
 				if (bit2num.count(bit) == 0) {
 					bitinfo_t info;
 					info.num = bit2info.size();
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 7ab7233c6..913855f48 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -44,46 +44,48 @@ struct OptReduceWorker
 		cells.erase(cell);
 
 		RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
-		sig_a.sort_and_unify();
-		sig_a.expand();
+		std::set<RTLIL::SigBit> new_sig_a_bits;
 
-		RTLIL::SigSpec new_sig_a;
-		for (auto &chunk : sig_a.chunks())
+		for (auto &bit : sig_a.to_sigbit_set())
 		{
-			if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) {
+			if (bit == RTLIL::State::S0) {
 				if (cell->type == "$reduce_and") {
-					new_sig_a = RTLIL::SigSpec(RTLIL::State::S0);
+					new_sig_a_bits.clear();
+					new_sig_a_bits.insert(RTLIL::State::S0);
 					break;
 				}
 				continue;
 			}
-			if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S1) {
+			if (bit == RTLIL::State::S1) {
 				if (cell->type == "$reduce_or") {
-					new_sig_a = RTLIL::SigSpec(RTLIL::State::S1);
+					new_sig_a_bits.clear();
+					new_sig_a_bits.insert(RTLIL::State::S1);
 					break;
 				}
 				continue;
 			}
-			if (chunk.wire == NULL) {
-				new_sig_a.append(chunk);
+			if (bit.wire == NULL) {
+				new_sig_a_bits.insert(bit);
 				continue;
 			}
 
 			bool imported_children = false;
-			for (auto child_cell : drivers.find(chunk)) {
+			for (auto child_cell : drivers.find(bit)) {
 				if (child_cell->type == cell->type) {
 					opt_reduce(cells, drivers, child_cell);
-					if (child_cell->connections["\\Y"].extract(0, 1) == chunk)
-						new_sig_a.append(child_cell->connections["\\A"]);
-					else
-						new_sig_a.append(RTLIL::State::S0);
+					if (child_cell->connections["\\Y"][0] == bit) {
+						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->connections["\\A"]).to_sigbit_set();
+						new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
+					} else
+						new_sig_a_bits.insert(RTLIL::State::S0);
 					imported_children = true;
 				}
 			}
 			if (!imported_children)
-				new_sig_a.append(chunk);
+				new_sig_a_bits.insert(bit);
 		}
-		new_sig_a.sort_and_unify();
+
+		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 
 		if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 090f7463a..9b8c35361 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -169,10 +169,9 @@ struct VlogHammerReporter
 		if (!ez.solve(y_vec, y_values))
 			log_error("Failed to find solution to SAT problem.\n");
 
-		expected_y.expand();
 		for (int i = 0; i < expected_y.size(); i++) {
 			RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0;
-			RTLIL::State expected_bit = expected_y.chunks().at(i).data.bits.at(0);
+			RTLIL::State expected_bit = expected_y[i].data;
 			if (model_undef) {
 				if (y_values.at(expected_y.size()+i))
 					solution_bit = RTLIL::State::Sx;
@@ -187,8 +186,7 @@ struct VlogHammerReporter
 						sat_bits += "x";
 					else
 						sat_bits += y_values.at(k) ? "1" : "0";
-					rtl_bits += expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" :
-							expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0";
+					rtl_bits += expected_y[k] == RTLIL::State::Sx ? "x" : expected_y[k] == RTLIL::State::S1 ? "1" : "0";
 				}
 				log_error("Found error in SAT model: y[%d] = %s, should be %s:\n   SAT: %s\n   RTL: %s\n        %*s^\n",
 						int(i), log_signal(solution_bit), log_signal(expected_bit),
@@ -288,11 +286,9 @@ struct VlogHammerReporter
 
 				if (module_name == "rtl") {
 					rtl_sig = sig;
-					rtl_sig.expand();
 					sat_check(module, recorded_set_vars, recorded_set_vals, sig, false);
 					sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
 				} else if (rtl_sig.size() > 0) {
-					sig.expand();
 					if (rtl_sig.size() != sig.size())
 						log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
 					for (int i = 0; i < SIZE(sig); i++)
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 24968aa2c..34becaee8 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -411,10 +411,8 @@ struct SatHelper
 		if (prove_asserts) {
 			RTLIL::SigSpec asserts_a, asserts_en;
 			satgen.getAsserts(asserts_a, asserts_en, timestep);
-			asserts_a.expand();
-			asserts_en.expand();
-			for (size_t i = 0; i < asserts_a.chunks().size(); i++)
-				log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks()[i]), log_signal(asserts_en.chunks()[i]));
+			for (int i = 0; i < SIZE(asserts_a); i++)
+				log("Import proof for assert: %s when %s.\n", log_signal(asserts_a[i]), log_signal(asserts_en[i]));
 			prove_bits.push_back(satgen.importAsserts(timestep));
 		}
 
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index e5055c9c4..4c3aec31d 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -130,11 +130,8 @@ namespace
 					RTLIL::SigSpec needleSig = conn.second;
 					RTLIL::SigSpec haystackSig = haystackCell->connections.at(portMapping.at(conn.first));
 
-					needleSig.expand();
-					haystackSig.expand();
-
 					for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
-						RTLIL::Wire *needleWire = needleSig.chunks().at(i).wire, *haystackWire = haystackSig.chunks().at(i).wire;
+						RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
 						if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
 							if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
 								return false;
@@ -156,7 +153,7 @@ namespace
 			int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = NULL)
 	{
 		SigMap sigmap(mod);
-		std::map<RTLIL::SigChunk, bit_ref_t> sig_bit_ref;
+		std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
 
 		if (sel && !sel->selected(mod)) {
 			log("  Skipping module %s as it is not selected.\n", id2cstr(mod->name));
@@ -192,10 +189,9 @@ namespace
 					for (auto &conn : cell->connections) {
 						RTLIL::SigSpec conn_sig = conn.second;
 						sigmap.apply(conn_sig);
-						conn_sig.expand();
-						for (auto &chunk : conn_sig.chunks())
-							if (chunk.wire != NULL)
-								sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)]++;
+						for (auto &bit : conn_sig)
+							if (bit.wire != NULL)
+								sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++;
 					}
 			}
 
@@ -220,39 +216,37 @@ namespace
 
 				RTLIL::SigSpec conn_sig = conn.second;
 				sigmap.apply(conn_sig);
-				conn_sig.expand();
 
-				for (size_t i = 0; i < conn_sig.chunks().size(); i++)
+				for (int i = 0; i < conn_sig.size(); i++)
 				{
-					auto &chunk = conn_sig.chunks()[i];
-					assert(chunk.width == 1);
+					auto &bit = conn_sig[i];
 
-					if (chunk.wire == NULL) {
+					if (bit.wire == NULL) {
 						if (constports) {
 							std::string node = "$const$x";
-							if (chunk.data.bits[0] == RTLIL::State::S0) node = "$const$0";
-							if (chunk.data.bits[0] == RTLIL::State::S1) node = "$const$1";
-							if (chunk.data.bits[0] == RTLIL::State::Sz) node = "$const$z";
+							if (bit == RTLIL::State::S0) node = "$const$0";
+							if (bit == RTLIL::State::S1) node = "$const$1";
+							if (bit == RTLIL::State::Sz) node = "$const$z";
 							graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0);
 						} else
-							graph.createConstant(cell->name, conn.first, i, int(chunk.data.bits[0]));
+							graph.createConstant(cell->name, conn.first, i, int(bit.data));
 						continue;
 					}
 
-					if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)] > max_fanout)
+					if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)] > max_fanout)
 						continue;
 
-					if (sel && !sel->selected(mod, chunk.wire))
+					if (sel && !sel->selected(mod, bit.wire))
 						continue;
 
-					if (sig_bit_ref.count(chunk) == 0) {
-						bit_ref_t &bit_ref = sig_bit_ref[chunk];
+					if (sig_bit_ref.count(bit) == 0) {
+						bit_ref_t &bit_ref = sig_bit_ref[bit];
 						bit_ref.cell = cell->name;
 						bit_ref.port = conn.first;
 						bit_ref.bit = i;
 					}
 
-					bit_ref_t &bit_ref = sig_bit_ref[chunk];
+					bit_ref_t &bit_ref = sig_bit_ref[bit];
 					graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i);
 				}
 			}
@@ -267,11 +261,10 @@ namespace
 				{
 					RTLIL::SigSpec conn_sig = conn.second;
 					sigmap.apply(conn_sig);
-					conn_sig.expand();
 
-					for (auto &chunk : conn_sig.chunks())
-						if (sig_bit_ref.count(chunk) != 0) {
-							bit_ref_t &bit_ref = sig_bit_ref[chunk];
+					for (auto &bit : conn_sig)
+						if (sig_bit_ref.count(bit) != 0) {
+							bit_ref_t &bit_ref = sig_bit_ref[bit];
 							graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
 						}
 				}
@@ -285,11 +278,10 @@ namespace
 			{
 				RTLIL::SigSpec conn_sig(wire);
 				sigmap.apply(conn_sig);
-				conn_sig.expand();
 
-				for (auto &chunk : conn_sig.chunks())
-					if (sig_bit_ref.count(chunk) != 0) {
-						bit_ref_t &bit_ref = sig_bit_ref[chunk];
+				for (auto &bit : conn_sig)
+					if (sig_bit_ref.count(bit) != 0) {
+						bit_ref_t &bit_ref = sig_bit_ref[bit];
 						graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
 					}
 			}
@@ -333,9 +325,8 @@ namespace
 			for (auto &conn : needle_cell->connections) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
-					sig.expand();
 					for (int i = 0; i < sig.size(); i++)
-					for (auto &port : sig2port.find(sig.chunks()[i])) {
+					for (auto &port : sig2port.find(sig[i])) {
 						RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1);
 						cell->connections.at(port.first).replace(port.second, bitsig);
 					}
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 1eb5c063b..034677d3b 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -29,75 +29,60 @@ extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*,
 
 static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	int width = cell->parameters.at("\\Y_WIDTH").as_int();
-
 	RTLIL::SigSpec sig_a = cell->connections.at("\\A");
-	sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool());
-	sig_a.expand();
-
 	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
-	sig_y.expand();
 
-	for (int i = 0; i < width; i++) {
+	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+
+	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = new RTLIL::Cell;
 		gate->name = NEW_ID;
 		gate->type = "$_INV_";
-		gate->connections["\\A"] = sig_a.chunks().at(i);
-		gate->connections["\\Y"] = sig_y.chunks().at(i);
+		gate->connections["\\A"] = sig_a[i];
+		gate->connections["\\Y"] = sig_y[i];
 		module->add(gate);
 	}
 }
 
 static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	int width = cell->parameters.at("\\Y_WIDTH").as_int();
-
 	RTLIL::SigSpec sig_a = cell->connections.at("\\A");
-	sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool());
-
 	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
 
+	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+
 	module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
 }
 
 static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	int width = cell->parameters.at("\\Y_WIDTH").as_int();
-
 	RTLIL::SigSpec sig_a = cell->connections.at("\\A");
-	sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
-
 	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
 
+	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+
 	module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
 }
 
 static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	int width = cell->parameters.at("\\Y_WIDTH").as_int();
-
 	RTLIL::SigSpec sig_a = cell->connections.at("\\A");
-	sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
-	sig_a.expand();
-
 	RTLIL::SigSpec sig_b = cell->connections.at("\\B");
-	sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool());
-	sig_b.expand();
-
 	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
-	sig_y.expand();
+
+	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+	sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
 
 	if (cell->type == "$xnor")
 	{
-		RTLIL::SigSpec sig_t = module->addWire(NEW_ID, width);
-		sig_t.expand();
+		RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
 
-		for (int i = 0; i < width; i++) {
+		for (int i = 0; i < SIZE(sig_y); i++) {
 			RTLIL::Cell *gate = new RTLIL::Cell;
 			gate->name = NEW_ID;
 			gate->type = "$_INV_";
-			gate->connections["\\A"] = sig_t.chunks().at(i);
-			gate->connections["\\Y"] = sig_y.chunks().at(i);
+			gate->connections["\\A"] = sig_t[i];
+			gate->connections["\\Y"] = sig_y[i];
 			module->add(gate);
 		}
 
@@ -111,13 +96,13 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$xnor") gate_type = "$_XOR_";
 	log_assert(!gate_type.empty());
 
-	for (int i = 0; i < width; i++) {
+	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = new RTLIL::Cell;
 		gate->name = NEW_ID;
 		gate->type = gate_type;
-		gate->connections["\\A"] = sig_a.chunks().at(i);
-		gate->connections["\\B"] = sig_b.chunks().at(i);
-		gate->connections["\\Y"] = sig_y.chunks().at(i);
+		gate->connections["\\A"] = sig_a[i];
+		gate->connections["\\B"] = sig_b[i];
+		gate->connections["\\Y"] = sig_y[i];
 		module->add(gate);
 	}
 }
@@ -125,8 +110,6 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	RTLIL::SigSpec sig_a = cell->connections.at("\\A");
-	sig_a.expand();
-
 	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
 
 	if (sig_y.size() == 0)
@@ -159,21 +142,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	while (sig_a.size() > 1)
 	{
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
-		sig_t.expand();
 
 		for (int i = 0; i < sig_a.size(); i += 2)
 		{
 			if (i+1 == sig_a.size()) {
-				sig_t.append(sig_a.chunks().at(i));
+				sig_t.append(sig_a[i]);
 				continue;
 			}
 
 			RTLIL::Cell *gate = new RTLIL::Cell;
 			gate->name = NEW_ID;
 			gate->type = gate_type;
-			gate->connections["\\A"] = sig_a.chunks().at(i);
-			gate->connections["\\B"] = sig_a.chunks().at(i+1);
-			gate->connections["\\Y"] = sig_t.chunks().at(i/2);
+			gate->connections["\\A"] = sig_a[i];
+			gate->connections["\\B"] = sig_a[i+1];
+			gate->connections["\\Y"] = sig_t[i/2];
 			last_output = &gate->connections["\\Y"];
 			module->add(gate);
 		}
@@ -202,26 +184,23 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 
 static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 {
-	sig.expand();
-
 	while (sig.size() > 1)
 	{
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
-		sig_t.expand();
 
 		for (int i = 0; i < sig.size(); i += 2)
 		{
 			if (i+1 == sig.size()) {
-				sig_t.append(sig.chunks().at(i));
+				sig_t.append(sig[i]);
 				continue;
 			}
 
 			RTLIL::Cell *gate = new RTLIL::Cell;
 			gate->name = NEW_ID;
 			gate->type = "$_OR_";
-			gate->connections["\\A"] = sig.chunks().at(i);
-			gate->connections["\\B"] = sig.chunks().at(i+1);
-			gate->connections["\\Y"] = sig_t.chunks().at(i/2);
+			gate->connections["\\A"] = sig[i];
+			gate->connections["\\B"] = sig[i+1];
+			gate->connections["\\Y"] = sig_t[i/2];
 			module->add(gate);
 		}
 
@@ -289,25 +268,18 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 
 static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	int width = cell->parameters.at("\\WIDTH").as_int();
-
 	RTLIL::SigSpec sig_a = cell->connections.at("\\A");
-	sig_a.expand();
-
 	RTLIL::SigSpec sig_b = cell->connections.at("\\B");
-	sig_b.expand();
-
 	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
-	sig_y.expand();
 
-	for (int i = 0; i < width; i++) {
+	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = new RTLIL::Cell;
 		gate->name = NEW_ID;
 		gate->type = "$_MUX_";
-		gate->connections["\\A"] = sig_a.chunks().at(i);
-		gate->connections["\\B"] = sig_b.chunks().at(i);
+		gate->connections["\\A"] = sig_a[i];
+		gate->connections["\\B"] = sig_b[i];
 		gate->connections["\\S"] = cell->connections.at("\\S");
-		gate->connections["\\Y"] = sig_y.chunks().at(i);
+		gate->connections["\\Y"] = sig_y[i];
 		module->add(gate);
 	}
 }
@@ -335,13 +307,8 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
 	RTLIL::SigSpec sig_s = cell->connections.at("\\SET");
-	sig_s.expand();
-
 	RTLIL::SigSpec sig_r = cell->connections.at("\\CLR");
-	sig_r.expand();
-
 	RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
-	sig_q.expand();
 
 	std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
 
@@ -349,9 +316,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 		RTLIL::Cell *gate = new RTLIL::Cell;
 		gate->name = NEW_ID;
 		gate->type = gate_type;
-		gate->connections["\\S"] = sig_s.chunks().at(i);
-		gate->connections["\\R"] = sig_r.chunks().at(i);
-		gate->connections["\\Q"] = sig_q.chunks().at(i);
+		gate->connections["\\S"] = sig_s[i];
+		gate->connections["\\R"] = sig_r[i];
+		gate->connections["\\Q"] = sig_q[i];
 		module->add(gate);
 	}
 }
@@ -362,12 +329,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 	char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 
 	RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
-
 	RTLIL::SigSpec sig_d = cell->connections.at("\\D");
-	sig_d.expand();
-
 	RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
-	sig_q.expand();
 
 	std::string gate_type = stringf("$_DFF_%c_", clk_pol);
 
@@ -376,8 +339,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 		gate->name = NEW_ID;
 		gate->type = gate_type;
 		gate->connections["\\C"] = sig_clk;
-		gate->connections["\\D"] = sig_d.chunks().at(i);
-		gate->connections["\\Q"] = sig_q.chunks().at(i);
+		gate->connections["\\D"] = sig_d[i];
+		gate->connections["\\Q"] = sig_q[i];
 		module->add(gate);
 	}
 }
@@ -390,18 +353,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
 	RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
-
 	RTLIL::SigSpec sig_s = cell->connections.at("\\SET");
-	sig_s.expand();
-
 	RTLIL::SigSpec sig_r = cell->connections.at("\\CLR");
-	sig_r.expand();
-
 	RTLIL::SigSpec sig_d = cell->connections.at("\\D");
-	sig_d.expand();
-
 	RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
-	sig_q.expand();
 
 	std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
 
@@ -410,10 +365,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 		gate->name = NEW_ID;
 		gate->type = gate_type;
 		gate->connections["\\C"] = sig_clk;
-		gate->connections["\\S"] = sig_s.chunks().at(i);
-		gate->connections["\\R"] = sig_r.chunks().at(i);
-		gate->connections["\\D"] = sig_d.chunks().at(i);
-		gate->connections["\\Q"] = sig_q.chunks().at(i);
+		gate->connections["\\S"] = sig_s[i];
+		gate->connections["\\R"] = sig_r[i];
+		gate->connections["\\D"] = sig_d[i];
+		gate->connections["\\Q"] = sig_q[i];
 		module->add(gate);
 	}
 }
@@ -430,12 +385,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK");
 	RTLIL::SigSpec sig_rst = cell->connections.at("\\ARST");
-
 	RTLIL::SigSpec sig_d = cell->connections.at("\\D");
-	sig_d.expand();
-
 	RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
-	sig_q.expand();
 
 	std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
 	std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
@@ -446,8 +397,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 		gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0;
 		gate->connections["\\C"] = sig_clk;
 		gate->connections["\\R"] = sig_rst;
-		gate->connections["\\D"] = sig_d.chunks().at(i);
-		gate->connections["\\Q"] = sig_q.chunks().at(i);
+		gate->connections["\\D"] = sig_d[i];
+		gate->connections["\\Q"] = sig_q[i];
 		module->add(gate);
 	}
 }
@@ -458,12 +409,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 	char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 
 	RTLIL::SigSpec sig_en = cell->connections.at("\\EN");
-
 	RTLIL::SigSpec sig_d = cell->connections.at("\\D");
-	sig_d.expand();
-
 	RTLIL::SigSpec sig_q = cell->connections.at("\\Q");
-	sig_q.expand();
 
 	std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
 
@@ -472,8 +419,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 		gate->name = NEW_ID;
 		gate->type = gate_type;
 		gate->connections["\\E"] = sig_en;
-		gate->connections["\\D"] = sig_d.chunks().at(i);
-		gate->connections["\\Q"] = sig_q.chunks().at(i);
+		gate->connections["\\D"] = sig_d[i];
+		gate->connections["\\Q"] = sig_q[i];
 		module->add(gate);
 	}
 }