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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 11:45:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 11:45:02 -0700 |
| commit | 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11 (patch) | |
| tree | 4919f2153ad547402f8dcc36421372567cbb34a8 /passes/opt | |
| parent | 6044fff074f026676312f047cfd5a7c862ff987f (diff) | |
| download | yosys-4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.tar.gz yosys-4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.tar.bz2 yosys-4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.zip | |
SigSet<Cell*> to use stable compare class
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_reduce.cc | 4 | ||||
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 6a8d8cabd..9850775af 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -37,7 +37,7 @@ struct OptReduceWorker int total_count; bool did_something; - void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell) + void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> &drivers, RTLIL::Cell *cell) { if (cells.count(cell) == 0) return; @@ -289,7 +289,7 @@ struct OptReduceWorker const IdString type_list[] = { ID($reduce_or), ID($reduce_and) }; for (auto type : type_list) { - SigSet<RTLIL::Cell*> drivers; + SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> drivers; pool<RTLIL::Cell*> cells; for (auto &cell_it : module->cells_) { diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 0bf74098a..8d4b6b14b 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -29,7 +29,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN SigMap assign_map, dff_init_map; -SigSet<RTLIL::Cell*> mux_drivers; +SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> mux_drivers; dict<SigBit, RTLIL::Cell*> bit2driver; dict<SigBit, pool<SigBit>> init_attributes; |