From 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Sep 2019 11:45:02 -0700
Subject: SigSet<Cell*> to use stable compare class

---
 passes/opt/opt_reduce.cc | 4 ++--
 passes/opt/opt_rmdff.cc  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 6a8d8cabd..9850775af 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -37,7 +37,7 @@ struct OptReduceWorker
 	int total_count;
 	bool did_something;
 
-	void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell)
+	void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> &drivers, RTLIL::Cell *cell)
 	{
 		if (cells.count(cell) == 0)
 			return;
@@ -289,7 +289,7 @@ struct OptReduceWorker
 			const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
 			for (auto type : type_list)
 			{
-				SigSet<RTLIL::Cell*> drivers;
+				SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> drivers;
 				pool<RTLIL::Cell*> cells;
 
 				for (auto &cell_it : module->cells_) {
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 0bf74098a..8d4b6b14b 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -29,7 +29,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 SigMap assign_map, dff_init_map;
-SigSet<RTLIL::Cell*> mux_drivers;
+SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> mux_drivers;
 dict<SigBit, RTLIL::Cell*> bit2driver;
 dict<SigBit, pool<SigBit>> init_attributes;
 
-- 
cgit v1.2.3