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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 08:22:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 08:22:23 -0700 |
| commit | 379f33af5489850ef8e2e58ef12ff5b22da87711 (patch) | |
| tree | 75f9d114509ede495afc7d29850e838ef1e7e384 /passes/opt | |
| parent | 9e31f01b343a9b246430419e81da647e75bd1626 (diff) | |
| download | yosys-379f33af5489850ef8e2e58ef12ff5b22da87711.tar.gz yosys-379f33af5489850ef8e2e58ef12ff5b22da87711.tar.bz2 yosys-379f33af5489850ef8e2e58ef12ff5b22da87711.zip | |
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index aca15e5f2..c4da613ab 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -745,16 +745,20 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == ID($shiftx) && GetSize(cell->getPort(ID::Y)) == 1) { + if (cell->type.in(ID($shiftx), ID($shift))) { SigSpec sig_a = assign_map(cell->getPort(ID::A)); int width; + bool trim_x = true; + bool trim_0 = cell->type == ID($shift); for (width = GetSize(sig_a); width > 1; width--) { - if (sig_a[width-1] != State::Sx) - break; + if ((trim_x && sig_a[width-1] == State::Sx) || + (trim_0 && sig_a[width-1] == State::S0)) + continue; + break; } if (width < GetSize(sig_a)) { - cover("opt.opt_expr.trim_shiftx"); + cover_list("opt.opt_expr.xbit", "$shiftx", "$shift", cell->type.str()); sig_a.remove(width, GetSize(sig_a)-width); cell->setPort(ID::A, sig_a); cell->setParam(ID(A_WIDTH), width); |