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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 08:06:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 08:06:24 -0700 |
| commit | 9e31f01b343a9b246430419e81da647e75bd1626 (patch) | |
| tree | 258f3e9349bcaf165d6d991f4a7fe2930686d8e5 /passes/opt | |
| parent | d0ffe7544cd3c808857f3a99bbf330de61c618f2 (diff) | |
| download | yosys-9e31f01b343a9b246430419e81da647e75bd1626.tar.gz yosys-9e31f01b343a9b246430419e81da647e75bd1626.tar.bz2 yosys-9e31f01b343a9b246430419e81da647e75bd1626.zip | |
Add cover()
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 7fdfa82bd..aca15e5f2 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -754,6 +754,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (width < GetSize(sig_a)) { + cover("opt.opt_expr.trim_shiftx"); sig_a.remove(width, GetSize(sig_a)-width); cell->setPort(ID::A, sig_a); cell->setParam(ID(A_WIDTH), width); |