Make liberal use of IdString.in()

4 files changed, 10 insertions, 10 deletions

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 7567d4657..8964171e6 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -94,8 +94,8 @@ struct OptMergeWorker
 		const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
 		dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
 
-		if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
-				cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
+		if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul",
+				"$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) {
 			alt_conn = *conn;
 			if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
 				alt_conn["\\A"] = conn->at("\\B");
@@ -103,13 +103,13 @@ struct OptMergeWorker
 			}
 			conn = &alt_conn;
 		} else
-		if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
+		if (cell->type.in("$reduce_xor", "$reduce_xnor")) {
 			alt_conn = *conn;
 			assign_map.apply(alt_conn.at("\\A"));
 			alt_conn.at("\\A").sort();
 			conn = &alt_conn;
 		} else
-		if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") {
+		if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) {
 			alt_conn = *conn;
 			assign_map.apply(alt_conn.at("\\A"));
 			alt_conn.at("\\A").sort_and_unify();
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 6511e091b..4b96fe524 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -84,7 +84,7 @@ struct OptMuxtreeWorker
 		//	.const_deactivated
 		for (auto cell : module->cells())
 		{
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				RTLIL::SigSpec sig_a = cell->getPort("\\A");
 				RTLIL::SigSpec sig_b = cell->getPort("\\B");
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index be6ac2d30..d712736c1 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -71,7 +71,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 		pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
 		pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
 	} else
-	if (cell->type == "$dffsr" || cell->type == "$dlatchsr") {
+	if (cell->type.in("$dffsr", "$dlatchsr")) {
 		pol_set = cell->parameters["\\SET_POLARITY"].as_bool() ? State::S1 : State::S0;
 		pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool() ? State::S1 : State::S0;
 	} else
@@ -137,7 +137,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$dffsr" || cell->type == "$dlatchsr")
+	if (cell->type.in("$dffsr", "$dlatchsr"))
 	{
 		cell->setParam("\\WIDTH", GetSize(sig_d));
 		cell->setPort("\\SET", sig_set);
@@ -624,7 +624,7 @@ struct OptRmdffPass : public Pass {
 						}
 				}
 
-				if (cell->type == "$mux" || cell->type == "$pmux") {
+				if (cell->type.in("$mux", "$pmux")) {
 					if (cell->getPort("\\A").size() == cell->getPort("\\B").size())
 						mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell);
 					continue;
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index c85c27427..7f66f749f 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -376,13 +376,13 @@ struct ShareWorker
 				continue;
 			}
 
-			if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") {
+			if (cell->type.in("$mul", "$div", "$mod")) {
 				if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4)
 					shareable_cells.insert(cell);
 				continue;
 			}
 
-			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
+			if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) {
 				if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8)
 					shareable_cells.insert(cell);
 				continue;