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| author | Claire Wolf <clifford@clifford.at> | 2020-01-29 17:01:24 +0100 |
|---|---|---|
| committer | Claire Wolf <clifford@clifford.at> | 2020-01-29 17:01:24 +0100 |
| commit | 1679682fa3ae18282b49452891282901a3548ecc (patch) | |
| tree | bb6c0b638623b62431805ea6b9ad8929a4be31ec /passes/opt | |
| parent | 4d0118d0c12d1f0f1604714ca10a49644a8ebee5 (diff) | |
| parent | e558b3284b346b76ac2c06a0f6d61c9d53cba70c (diff) | |
| download | yosys-1679682fa3ae18282b49452891282901a3548ecc.tar.gz yosys-1679682fa3ae18282b49452891282901a3548ecc.tar.bz2 yosys-1679682fa3ae18282b49452891282901a3548ecc.zip | |
Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Also some minor fixes to the original PR.
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_reduce.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 09f6e12e9..f74655d1c 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -44,9 +44,10 @@ struct OptReduceWorker cells.erase(cell); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); + sig_a.sort_and_unify(); pool<RTLIL::SigBit> new_sig_a_bits; - for (auto &bit : sig_a.to_sigbit_set()) + for (auto &bit : sig_a) { if (bit == RTLIL::State::S0) { if (cell->type == ID($reduce_and)) { @@ -86,6 +87,7 @@ struct OptReduceWorker } RTLIL::SigSpec new_sig_a(new_sig_a_bits); + new_sig_a.sort_and_unify(); if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); |