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| author | Kaj Tuomi <kaj.tuomi@siru.fi> | 2017-10-17 09:58:01 +0300 |
|---|---|---|
| committer | Kaj Tuomi <kaj.tuomi@siru.fi> | 2017-10-17 09:58:01 +0300 |
| commit | e558b3284b346b76ac2c06a0f6d61c9d53cba70c (patch) | |
| tree | e99f93f1b918ac40c62b3f10b2be16ae89a57db3 /passes/opt | |
| parent | 778df553eda678c31eed91f16728fab84a8c8c1d (diff) | |
| download | yosys-e558b3284b346b76ac2c06a0f6d61c9d53cba70c.tar.gz yosys-e558b3284b346b76ac2c06a0f6d61c9d53cba70c.tar.bz2 yosys-e558b3284b346b76ac2c06a0f6d61c9d53cba70c.zip | |
Fix input vector for reduce cells. Infinite loop fixed.
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_reduce.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index eb9d02ad5..8126f3c0d 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -44,6 +44,7 @@ struct OptReduceWorker cells.erase(cell); RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + sig_a.sort_and_unify(); pool<RTLIL::SigBit> new_sig_a_bits; for (auto &bit : sig_a.to_sigbit_set()) @@ -86,6 +87,7 @@ struct OptReduceWorker } RTLIL::SigSpec new_sig_a(new_sig_a_bits); + new_sig_a.sort_and_unify(); if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); |