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authorClifford Wolf <clifford@clifford.at>2014-07-31 16:38:54 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-31 16:38:54 +0200
commitcdae8abe16847c533171fed111beea7b52202cce (patch)
treebf8dddb4a4ca4d70c83603ef61b2d22cb95d153a /passes/fsm/fsmdata.h
parentb5a9e51b966abdfedc9309defa79b5141928e84a (diff)
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Renamed port access function on RTLIL::Cell, added param access functions
Diffstat (limited to 'passes/fsm/fsmdata.h')
-rw-r--r--passes/fsm/fsmdata.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 8f0e5d621..7a44dd452 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -141,13 +141,13 @@ struct FsmData
log("\n");
log(" Input signals:\n");
- RTLIL::SigSpec sig_in = cell->get("\\CTRL_IN");
+ RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
for (int i = 0; i < SIZE(sig_in); i++)
log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
- RTLIL::SigSpec sig_out = cell->get("\\CTRL_OUT");
+ RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
for (int i = 0; i < SIZE(sig_out); i++)
log(" %3d: %s\n", i, log_signal(sig_out[i]));