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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:12:38 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:12:38 -0700 |
commit | 71649969213863b2695f1c51956886fc7879c3e6 (patch) | |
tree | 7fb2cf4be9d2d5628dc4c54a8c9161fd57e62bfd /passes/fsm/fsm_extract.cc | |
parent | e6d5147214bd157c457654dc46547775ec6ad324 (diff) | |
download | yosys-71649969213863b2695f1c51956886fc7879c3e6.tar.gz yosys-71649969213863b2695f1c51956886fc7879c3e6.tar.bz2 yosys-71649969213863b2695f1c51956886fc7879c3e6.zip |
RTLIL::S{0,1} -> State::S{0,1}
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
-rw-r--r-- | passes/fsm/fsm_extract.cc | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 6095eaf30..a85c3bec0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -168,7 +168,7 @@ undef_bit_in_next_state: ctrl_in_bit_indices[ctrl_in[i]] = i; for (auto &it : ctrl_in_bit_indices) - if (tr.ctrl_in.bits.at(it.second) == RTLIL::S1 && exclusive_ctrls.count(it.first) != 0) + if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0) for (auto &dc_bit : exclusive_ctrls.at(it.first)) if (ctrl_in_bit_indices.count(dc_bit)) tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa; @@ -216,13 +216,13 @@ undef_bit_in_next_state: ce.push(); dont_care.append(undef); ce.set(undef, constval.as_const()); - if (exclusive_ctrls.count(undef) && constval == RTLIL::S1) + if (exclusive_ctrls.count(undef) && constval == State::S1) for (auto &bit : exclusive_ctrls.at(undef)) { RTLIL::SigSpec bitval = bit; - if (ce.eval(bitval) && bitval != RTLIL::S0) + if (ce.eval(bitval) && bitval != State::S0) goto found_contradiction_1; else - ce.set(bit, RTLIL::S0); + ce.set(bit, State::S0); } find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); found_contradiction_1: @@ -231,21 +231,21 @@ undef_bit_in_next_state: else { ce.push(), ce_nostop.push(); - ce.set(undef, RTLIL::S0); - ce_nostop.set(undef, RTLIL::S0); + ce.set(undef, State::S0); + ce_nostop.set(undef, State::S0); find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); ce.pop(), ce_nostop.pop(); ce.push(), ce_nostop.push(); - ce.set(undef, RTLIL::S1); - ce_nostop.set(undef, RTLIL::S1); + ce.set(undef, State::S1); + ce_nostop.set(undef, State::S1); if (exclusive_ctrls.count(undef)) for (auto &bit : exclusive_ctrls.at(undef)) { RTLIL::SigSpec bitval = bit; - if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != RTLIL::S0) + if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != State::S0) goto found_contradiction_2; else - ce.set(bit, RTLIL::S0), ce_nostop.set(bit, RTLIL::S0); + ce.set(bit, State::S0), ce_nostop.set(bit, RTLIL::S0); } find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); found_contradiction_2: @@ -263,8 +263,8 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width); RTLIL::Const reset_state(RTLIL::State::Sx, wire->width); - RTLIL::SigSpec clk = RTLIL::S0; - RTLIL::SigSpec arst = RTLIL::S0; + RTLIL::SigSpec clk = State::S0; + RTLIL::SigSpec arst = State::S0; bool clk_polarity = true; bool arst_polarity = true; @@ -371,8 +371,8 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); fsm_cell->setPort("\\CLK", clk); fsm_cell->setPort("\\ARST", arst); - fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? RTLIL::S1 : RTLIL::S0; - fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? RTLIL::S1 : RTLIL::S0; + fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0; + fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0; fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort("\\CTRL_OUT", ctrl_out); fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); |