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| author | Clifford Wolf <clifford@clifford.at> | 2015-03-25 19:46:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-03-25 19:46:12 +0100 |
| commit | a923a63a892b8f0c39aa740c8fe207462fe2d8c8 (patch) | |
| tree | ad5a170887620f00c91672c3d2394306527d7641 /passes/cmds | |
| parent | e468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9 (diff) | |
| download | yosys-a923a63a892b8f0c39aa740c8fe207462fe2d8c8.tar.gz yosys-a923a63a892b8f0c39aa740c8fe207462fe2d8c8.tar.bz2 yosys-a923a63a892b8f0c39aa740c8fe207462fe2d8c8.zip | |
Ignore celldefine directive in verilog front-end
Diffstat (limited to 'passes/cmds')
0 files changed, 0 insertions, 0 deletions