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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 11:45:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-12 11:45:02 -0700 |
| commit | 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11 (patch) | |
| tree | 4919f2153ad547402f8dcc36421372567cbb34a8 /passes/cmds | |
| parent | 6044fff074f026676312f047cfd5a7c862ff987f (diff) | |
| download | yosys-4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.tar.gz yosys-4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.tar.bz2 yosys-4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.zip | |
SigSet<Cell*> to use stable compare class
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/scc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 99f4fbae8..0a4f9e98d 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -116,7 +116,7 @@ struct SccWorker } SigPool selectedSignals; - SigSet<RTLIL::Cell*> sigToNextCells; + SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sigToNextCells; for (auto &it : module->wires_) if (design->selected(module, it.second)) |