From 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Sep 2019 11:45:02 -0700
Subject: SigSet<Cell*> to use stable compare class

---
 passes/cmds/scc.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/cmds')

diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 99f4fbae8..0a4f9e98d 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -116,7 +116,7 @@ struct SccWorker
 		}
 
 		SigPool selectedSignals;
-		SigSet<RTLIL::Cell*> sigToNextCells;
+		SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sigToNextCells;
 
 		for (auto &it : module->wires_)
 			if (design->selected(module, it.second))
-- 
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