From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- passes/cmds/connect.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/cmds/connect.cc') diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index f8f9e0590..dcd5fc96b 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) for (auto &port : it.second->connections) -- cgit v1.2.3