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| author | clairexen <claire@symbioticeda.com> | 2020-05-29 16:52:11 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-29 16:52:11 +0200 |
| commit | 0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3 (patch) | |
| tree | 2af754e54f6bd38da670fadd9fac7aaa6a1b48d3 /manual/CHAPTER_StateOfTheArt/simlib_yosys.v | |
| parent | 94c10353897c6b2b3f960bdd6647a5da9c1d9f2c (diff) | |
| parent | 66d0ed2bcc7195aab5b107b2536e6818fe5b244c (diff) | |
| download | yosys-0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3.tar.gz yosys-0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3.tar.bz2 yosys-0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3.zip | |
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
ast/simplify: don't bitblast async ROMs declared as `logic`
Diffstat (limited to 'manual/CHAPTER_StateOfTheArt/simlib_yosys.v')
0 files changed, 0 insertions, 0 deletions