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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:16:56 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:16:56 +0200 |
| commit | 0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47 (patch) | |
| tree | 03109f81a698f429ef9600a73f1053d7f51fdd64 /manual/APPNOTE_012_Verilog_to_BTOR.tex | |
| parent | 92e705cb51d8c8f6d9f1550ed103b677a2447c93 (diff) | |
| download | yosys-0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47.tar.gz yosys-0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47.tar.bz2 yosys-0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47.zip | |
Use HTTPS for website links, gatecat email
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
Diffstat (limited to 'manual/APPNOTE_012_Verilog_to_BTOR.tex')
| -rw-r--r-- | manual/APPNOTE_012_Verilog_to_BTOR.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index ebaa3e420..a96e26503 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -411,7 +411,7 @@ verification benchmarks with or without memories from Verilog designs. \bibitem{yosys} Clifford Wolf. The Yosys Open SYnthesis Suite. \\ -\url{http://yosyshq.net/yosys/} +\url{https://yosyshq.net/yosys/} \bibitem{boolector} Robert Brummayer and Armin Biere, Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays\\ |