From f0afd65035fefebdea8edbd00c916c5f33e8a634 Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Sun, 23 Feb 2020 07:19:52 +0000
Subject: Closes #1717. Add more precise Verilog source location information to
 AST and RTLIL nodes.

---
 kernel/rtlil.cc | 2 --
 1 file changed, 2 deletions(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 5d7e61901..06181b763 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3924,8 +3924,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
 	cover("kernel.rtlil.sigspec.parse");
 
 	AST::current_filename = "input";
-	AST::use_internal_line_num();
-	AST::set_line_num(0);
 
 	std::vector<std::string> tokens;
 	sigspec_parse_split(tokens, str, ',');
-- 
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