From a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 15 Nov 2016 12:42:43 +0100
Subject: Remember global declarations and defines accross read_verilog calls

---
 kernel/rtlil.cc | 2 ++
 kernel/rtlil.h  | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 66bbf0427..7693e3052 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -306,6 +306,8 @@ RTLIL::Design::~Design()
 		delete it->second;
 	for (auto n : verilog_packages)
 		delete n;
+	for (auto n : verilog_globals)
+		delete n;
 }
 
 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 9430dcb36..8dd8fcca3 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -793,7 +793,8 @@ struct RTLIL::Design
 
 	int refcount_modules_;
 	dict<RTLIL::IdString, RTLIL::Module*> modules_;
-	std::vector<AST::AstNode*> verilog_packages;
+	std::vector<AST::AstNode*> verilog_packages, verilog_globals;
+	dict<std::string, std::pair<std::string, bool>> verilog_defines;
 
 	std::vector<RTLIL::Selection> selection_stack;
 	dict<RTLIL::IdString, RTLIL::Selection> selection_vars;
-- 
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