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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-11 16:53:54 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-12 01:22:06 +0100 |
| commit | d019b4e6810bce37bd3477bb365288cae2a572b2 (patch) | |
| tree | 018b64ae47f1161c3da42e88a4d4113a12aa1db8 /kernel/rtlil.h | |
| parent | 21fbdb6638bc00758dfe7aaac93c5805160168d5 (diff) | |
| download | yosys-d019b4e6810bce37bd3477bb365288cae2a572b2.tar.gz yosys-d019b4e6810bce37bd3477bb365288cae2a572b2.tar.bz2 yosys-d019b4e6810bce37bd3477bb365288cae2a572b2.zip | |
rtlil: Dump empty connections when whole module is selected.
Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires. This makes debugging rather confusing.
Diffstat (limited to 'kernel/rtlil.h')
0 files changed, 0 insertions, 0 deletions