From b45d06d7a334c4b18e44793b33aaffcaf1f04b21 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 17 Jun 2019 12:54:24 -0700
Subject: Fix leak removing cells during ABC integration; also preserve attr

---
 kernel/rtlil.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'kernel/rtlil.h')

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f4fcf5dcf..4a0f8b4f8 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1040,6 +1040,7 @@ public:
 	// Removing wires is expensive. If you have to remove wires, remove them all at once.
 	void remove(const pool<RTLIL::Wire*> &wires);
 	void remove(RTLIL::Cell *cell);
+	dict<RTLIL::IdString, RTLIL::Cell*>::iterator remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it);
 
 	void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
 	void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
-- 
cgit v1.2.3