From 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 11 Oct 2018 23:33:31 +0200
Subject: Synthesis support for SystemVerilog interfaces

This time doing the changes mostly in AST before RTLIL generation
---
 kernel/rtlil.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'kernel/rtlil.h')

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 027faf416..8a2b0a4f3 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -907,7 +907,9 @@ public:
 	Module();
 	virtual ~Module();
 	virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false);
+	virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail = false);
 	virtual size_t count_id(RTLIL::IdString id);
+	virtual void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces);
 
 	virtual void sort();
 	virtual void check();
-- 
cgit v1.2.3